In this configuration
simulate this circuit – Schematic created using CircuitLab
if the two pMOS are equal, they provide the same drain current to both the branches: suppose that Vbias is chosen so that the drain current will have a certain (constant) value Ibias. Moreover, if a new pMOS is added and connected at the same Vdd and with the same gate potential Vbias, it will generate the same drain current as M1 and M2.
But often the current mirror configuration is used:
where the drain current of M1 is Ibias (and it is the drain current of any other transistor equal to M1 and connected in the same way).
I think that the two configurations (with appropriate Ibias and Vbias values) are equivalent.
My questions are:
- is the second configuration the most common in CMOS circuits? I found it more often than the former;
- if yes or if not, why?
Best Answer
In your first circuit, it's uncertain what output current you'll get for a given input voltage. First, because if you build this circuit on several chips, the PMOS behavior will not be identical from chip to chip. Also because as the temperature chagnes the PMOS device behavior will change.
In the second circuit, you know the output current will be essentially identical to the input current, regardless of variation of the MOSFET performance. The trick then is just to make a current source for the input that is insensitive to process and temperature variations.