Electronic – Digital sample and hold synced with a CLK

clockdigital-logicsample and hold

So I though this should be pretty straightforward, but apparently it's not.

Supposed we have a digital async input signal and a CLK. I want to sample the given input signal on every rising (or falling edge) of the CLK signal and output the value of the input signal when CLK event occured. I do not care about the intermediate states. I just want to have a signal that replicates the state of the input signal at a clock event and keeps that state until the next clock even.

Here is a diagram in case I am not clear enough:

I am sure that there is a simple IC (possibly from the 74xx series) that does exactly this, however, I cannot seem to come across one.

Thank you very much!

Best Answer

A D latch will do exactly what you want. The prototypical version is the 7474, though there are plenty of other part numbers that group them into quads, octals, add output or clock enables etc.

Some of the comments discuss what happens when the data changes on a clock edge. There are three possible outcomes. The first two are that you get the data it was, or you get the data it changes to. One of these two is overwhelmingly likely.

However a third rare possibility is that you get an output that cannot be interpreted as a valid logic output. It may be a middle state between the highest valid '0' and the lowest valid '1' that persists for longer than the expected propagation delay (\$T_p\$), or it could be an otherwise valid state that changes spontaneously later than \$T_p\$. This is metastability, which can only occur if you violate the setup and hold times of the D-latch. It cannot be avoided, but it can be designed down to a vanishingly small probability of occurring, by ensuring that you wait long enough after the initial sampling edge before trying to use the data. The chance of a bad logic output persisting falls exponentially as the delay increases. This is commonly done by adding at least a second, and sometimes more, further latches in a pipeline after the initial one. With enough latency, the probability can be pushed down to 'once in 10x the age of the universe', by which time you can reasonably regard it as 'solved'.

Related Solutions

Electronic – Slow clock edge causing issues with D flip flop behavior

You have unfortuantely run into a relatively subtle problem with this particular flip-flop. (BTW, this is not metastability; that's a different problem.) It's designed to operate at high speed over a wide range of supply voltages, and one of the compromises made in its design is that it has a rather strict requirement on the clock input transition speed.

If you look at section 9 of the datasheet, the input transition rate is given as 10 ns/V maximum. This means that you need to make the clock rise or fall by 5 volts in no more than 50 ns in order for the chip to operate correctly. With an RC time constant of 10 ms, you are about 6 orders of magnitude too slow.

Enable clock for a state machine

So this code generates a 200 Hz clock based on a 100 Mhz clock.

We note that: 100 MHz / 500000 = 200 Hz

So, we need to take our 100 Mhz clock, and every 500000 cycles, we would have a full cycle of the 200 Hz clock that we would like to generate. Since we want the high time and low time to be the same, we know that we should oscillate the new clock every 500000 / 2 cycles.

From the perspective of the code, we will use hexadecimal, so it's worth noting that 500000 / 2 == 0x3D090.

architecture foo of blah is
    signal clk_200Hz : std_logic := '0';
    signal counter : unsigned(19 downto 0) := x"00000";
begin

    clkdiv : process (clk_100Mhz)
    begin
        if rising_edge(clk_100Mhz) then
            if counter = x"00000" then
                counter <= X"3D090"
                clk_200Hz <= not clk_200Hz;
            else
                counter <= counter - 1;
            end if;
        end if;
    end process clkdiv;

end architecture;

Best Answer

Related Solutions

Electronic – Slow clock edge causing issues with D flip flop behavior

Enable clock for a state machine

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