I am trying to route a pic32 chip to a 128kB SRAM chip and having a bit of a hard time getting all 17 address lines and all 8 data lines connected. I am trying to tie the first 16 address pins to portB pins 0-15 and the data pins to portD 0-7.
After thinking about it for a while I realized that I am probably making my life more difficult by trying to line up rb0 with a0, rb1 with a1, etc. All I really want to be able to do is write a 16 bit value to portB and have the majority of the address loaded and ready. If I make pin assignments based on ease of routing, the logical address will be different between the mcu and the ram, but it should at least be consistent. Since nothing else needs to communicate with the RAM, I don't think it will be a problem if the mcu asks for address 0x101 and the RAM gives it address 0x110.
However, I wonder if it is a good idea. If there is some structure internal to the RAM designed to make sequential reads more efficient, or something like that, then I may want to go to the trouble of routing them 1:1. The pins arrangement on both chips fees somewhat random to me, so it would make it a lot easier on me if I could ignore the particular numbers. Is there any good reason why I should or should not do that?
Best Answer
In this case it seems wholly acceptable to interchange data bits and to interchange address bits. This is not universally the case, as you allude to in your question.
In this case the device is a static RAM - a quick flick through the AS6C1008 datasheet did not indicate any ability to do fast acceses of any sort or any address related timing dependancies.
General:
Some dynamic memories allow data bursting by latching in a high portion of the address and then sequencing low address bits. This may correspond to published logical row and column structure or to some arcane inner mechnism not obviously apparent externally. In such cases you need to stick to what the data sheet says in order to avoid storage failures.
Some early dynamic memories relied on address sequencing and access timing to achieve memory cell refreshing. You are unlikely to meet many of any of these nowadays.
Some memories (flash, eerom, some other) have lifetimes which are dependent on number of accesses, which may be per access (read or write) or more usually only per write, and may be per memory location or per some subset of memory cells. In the latter case, if you scramble address lines you may interfere with wear-levelling algorithms. This is only going to be a potential problem with fairly specialist devices and data sheets are liable to be reasonably clear on requirements