Electronic – First Time Using Integrated Circuits

Here is a simplistic explanation:

The D-type latch shown is a positive edge sampling type latch - Note the triangle indication on the clock input. This means it only reads data placed on the D input, at the time when the CLK signal is at its rising edge.

• So at first rising edge of CLK signal, TA samples the value at D, copies it to Q.
  • TB, TC and TD at the instant of this edge, do not have any meaningful value, they just read and latch (put on Q) whatever arbitrary value was at their input previously.
• At second rising edge of CLK, TA samples whatever fresh value is at D.
  • At the same time, TB samples and latches the value placed on TA's Q pin from previous cycle.
  • Values at TC and TD remain arbitrary "meaningless data", ignore them for now.
• At third rising edge, TA samples latest value, TB picks up TA's previous value, and TC picks up TB's previous value.
  • Value at TD is still to be ignored as "meaningless data".
• At fourth rising edge, TA samples afresh, TB reads TA's previous, TC reads TB, and TD reads TC.
  • At this time, the data that had been asserted on the data input line in the beginning, is showing on the output Q of TD - It has been "shifted" during the four rising edges of the clock, from left to right.
  • Outputs of TA, TB, TC and TD are now known, meaningful bits of data.
• At every following rising edge of CLK, the bits keep getting shifted left to right, TA --> TB --> TC --> TD --> out.

That is how the arrangement of latches you have shown, acts as a "shift" register: The values keep shifting left to right once per clock cycle's rising edge.

I will give you the Discret circuit diagram of LM311

and a link of LM integrated circuits list http://en.wikipedia.org/wiki/List_of_LM-series_integrated_circuits