Electronic – Signal propagation when observing integrated circuits

integrated-circuit

Consider this image:
4-digit serial shift register, based on D-latches

It says "4-digit serial shift register, based on D-type latches" (please correct me if this is not a valid terminology). Clearly, I can't understand a property of D-latch to hold back an input signal for 1 CLK cycle. Is it correct assumption that we should observe signal propagation starting from N-th (4th in this case) latch and going left until 1st one?
I mean, if we look from left to right, the register does not really shift, on the first high CLK, it just fills up with all "1"s.

UPDATE:
Basically, an essence of my question is – what goes first: D(k)->Q(k), or Q(k-1)->D(k)?

Best Answer

Here is a simplistic explanation:

The D-type latch shown is a positive edge sampling type latch - Note the triangle indication on the clock input. This means it only reads data placed on the D input, at the time when the CLK signal is at its rising edge.

  • So at first rising edge of CLK signal, TA samples the value at D, copies it to Q.
    • TB, TC and TD at the instant of this edge, do not have any meaningful value, they just read and latch (put on Q) whatever arbitrary value was at their input previously.
  • At second rising edge of CLK, TA samples whatever fresh value is at D.
    • At the same time, TB samples and latches the value placed on TA's Q pin from previous cycle.
    • Values at TC and TD remain arbitrary "meaningless data", ignore them for now.
  • At third rising edge, TA samples latest value, TB picks up TA's previous value, and TC picks up TB's previous value.
    • Value at TD is still to be ignored as "meaningless data".
  • At fourth rising edge, TA samples afresh, TB reads TA's previous, TC reads TB, and TD reads TC.
    • At this time, the data that had been asserted on the data input line in the beginning, is showing on the output Q of TD - It has been "shifted" during the four rising edges of the clock, from left to right.
    • Outputs of TA, TB, TC and TD are now known, meaningful bits of data.
  • At every following rising edge of CLK, the bits keep getting shifted left to right, TA --> TB --> TC --> TD --> out.

That is how the arrangement of latches you have shown, acts as a "shift" register: The values keep shifting left to right once per clock cycle's rising edge.

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