I have this error when trying to compile my VHDL code. The purpose of the code is to multiply a 2 bit constant K by some 4-bit number in memory. There are some similar posts here with the same error, but I have been unable to solve the problem even after using those posts. I thought the problem might be I need to make K unsigned, but converting it still gives the same problem. I am stuck, so any ideas are welcomed
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ROM_ent is
port (CLK : in std_logic;
RE : in std_logic;
K : in std_logic_vector(1 downto 0);
ADDR : in std_logic_vector(3 downto 0);
RESULT : out std_logic_vector(3 downto 0));
end ROM_ent;
architecture ROM_arch of ROM_ent is
type ROM is array (0 to 15) of std_logic_vector(3 downto 0);
constant Content: ROM := (
0=>"0000",
1=>"0001",
2=>"0010",
3=>"0011",
4=>"0100",
5=>"0101",
6=>"0110",
7=>"0111",
8=>"1000",
9=>"1001",
10=>"1010",
11=>"1011",
12=>"1100",
13=>"1101",
14=>"1110",
15=>"1111",
others=>"0000");
begin
process(CLK,RE,K)
begin
--if (CLK'event and CLK = '1') then
if (rising_edge(CLK)) then
if (RE = '1') then
RESULT <= Content(to_integer(unsigned(ADDR))) * K; --Gives error, 0 definitions of "*" operator
--RESULT <= Content(to_integer(unsigned(ADDR))); --This works fine (but doesnt do what I want obviously
else
RESULT <= "ZZZZ";
end if;
end if;
end process;
end ROM_arch;
Best Answer
VHDL is strictly typed language as you know. You have a bit type conversion problem in that statement you assign to
RESULT. It should be -Also the
RESULTshould be of size 6 bits. because you are multiplying 4 bits by 2 bits.Some suggestions:
No need of
REandKin the sensitivity list.You can avoid that else part for
REand simply latch the last result obtained.