Electronic – FPGA Performance of Routing

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I am trying to learn more about the performance of different routings in my design using Xilinx ISE. I've figured out how to move logic around by changing which CLB/Slice holds which piece of using the User Constraint file. Is there a way to manipulate the routing? Or, at the very least somewhere I can get it to give me a text description of the routing paths?

Further details:
I have implemented a simple AND gate in a spartan3E_100 and moved around the IOBs and the LUT which holds the logic. Every time I do so I look in the FPGA editor and the chosen routing is completely different. I'm sure it figures out the optimal but what I would like to do is modify the routing then look at how the performance changes. Is that possible? Second, is there any way to get a text description of the routing similar to the the info given in the UCF/PCF file?

Best Answer

Explicit 'hands-on' control of the routing sounds like a good idea, but it isn't.

Think back to the days when assembler programmers could squeeze a little bit more performance out of an algorithm by using manual assembly code instead of a compiler. There's only so much complexity you can think your way through. As the target becomes more complex, branch-prediction tables, multiple cores, deep execution pipelines, microthreading, that becomes impractical. I am writing here as somebody who wrote assembly code for a TI C6000 DSP, 8 execution units and a 5 deep pipeline for memory load/save, nightmare!

Only enthusiastic hobbyists write assembler these days, people who want to get the job done learn how to constrain, and to help, the compiler.

Anyhow, routing involves multiple resource types (long lines, half lines, straight through a mux, adjacent local lines, to mention but a few), multiple timing constraints (only a few of which are critical) and a lot of both.

The bottom line is that if you are laying out a single D latch, you can probably see your way round the routing. If you are doing anything of a worthwhile size, then you do not want to be, and cannot be, driving the routing directly. What you want to be doing is constraining, and helping, the routing optimiser. How?

Understand your timing constraints. Understand which are critical, and which are not. Don't over constrain for safety, the router is already taking account of worst case process with worst case voltage and temperature, that's why the timing tables are so humungeous. If you over-constrain, the router will struggle more. Only tightly constrain the critical lines.

Use floorplanning, this is where you can intervene with a bit of human 'I can see what I want' expertise. The placer doesn't always get it right. If the router fails, see what the placer has done, and if necessary, move some blocks from 'stupid' positions for a more sensible placing. Then let the router run again. Iterate that cycle, but let the router do its own thing.

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Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Electronic – Setting single unused pin in Xilinx ISE

You want them to output low, so go ahead and make them outputs in your VHDL. Then they won't get optimized out.

A single net called "RESERVED(xx downto 0)" would do it. Tie it low in your VHDL, and constrain it to the unused pins just as you would any other signal.

This is the most portable way, really.

Best Answer

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