This is probably a silly question but I figured this might be worth another question instead of adding it onto my other one.
Referring to this question (About an SR latches first Q state)
What is the beginning state for Q in a SR latch?
Lets pretend we have an AND gate (or really any kind of gate).
Inputs with A and B and Output Y.
Now lets pretend I send a Signal to A and B. What is the Output of the gates Initial Value? Like is Y always set to 0? Like when the computer is first turned on?
Like for example a NAND is 1 when both inputs are zero……so we do always assume the NAND gates output is 1 like when we first turn on a computer, or it receives it's first signal?
or for instance lets say a NAND gate for instance, and I send a 1 through input A, and a 1 through input B…..lets say (for some reason) the A gets there faster…..is the output 0 for a second then switches to 1….or was it 1 before (since technically both inputs were zero before?)
I guess looking at the transistor diagram might make more sense, but I guess the "timing" of Gates and SR latches has me a bit confused at what the outputs are "initially set" to.
Best Answer
We don't normally talk about a NAND gate having "state". It just responds to its inputs.
Since a NAND gate usually can respond to its inputs within a few nanoseconds, while power supply voltages typically take at least a few milliseconds to come up to valid levels during turn-on, the "state" of the NAND gates output immediately after start-up is rarely relevant.
In general during start-up there will be some time when the voltage rises to the point where the circuit is basically functional, but is not guaranteed to be functional. A NAND gate will start to respond to its inputs during this time and should be completely in sync with its inputs by the time the power supply voltage reaches the minimum voltage for guaranteed operation.
This can happen, and it is called a "glitch". A typical case is when A is switching from 1 to 0 and B is switching from 0 to 1. The output to the prior inputs is 0, and the output to the final inputs is 0, but it's possible to see a 1 asserted for a brief time during the transition if the change in A arrives first.
This is why designing syncronous logic is in many ways simpler than designing combinatorial logic. In syncronous logic we can arrange the timing so that the next flip-flop downstream never has a clock edge arrive during the time when the upstream logic might glitch, so the glitch never propagates through to be seen at the final outputs of the system.