Electronic – hold time violation

digital-logicflipfloptiming

I am currently reading about Pulsed Latch Circuit. And there is a frequent mention of "hold time violation". Like:

For latch, "…data must be held for a longer period of time,
increasing the likely number of hold time violations".

Please explain what hold time violation is in the context of Latches.

Best Answer

A edge-triggered latch (flipflop) ideally samples the data line instantaneously on one of the edges of the clock. However, nothing is truly instantaneous, so the data must be valid for some finite amount of time around the clock edge. The time it must be fixed before the clock edge is called the setup time, and the time it must be fixed after the clock edge is called the hold time.

Added:

Hold time violation is a violation of the hold time requirement. If the datasheet says the minimum required hold time is 10 ns and you change the data 5 ns after the clock edge, then you have committed a hold time violation and there is no guarantee which data value will end up on the flipflop output.