# Electronic – Clocked edge-triggered timing (contamination delay)

clockcomputer-architecturedigital-logicflipflopregister

I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is assumed to be greater than its hold time, "giving it the important property that its inputs and outputs can be read and written simultaneously (that is, by similar devices sharing the same clock input)".

But I didn't quite understand this statement. As far as I know (I'm very new to this subject), contamination delay is a minimum time, measured after the active clock edge, during which the output remains valid after the input has changed (measured after the active clock edge), and hold time is a minimum time requirement measured from the active clock edge, during which the input data has to be kept stable. Why is contamination delay of register greater than the hold time, and how exactly does this fact allow it to be read and written simultaneously? Could someone give a more detailed explanation?

Update: I understand basically the importance of having contamination delay greater than the hold time in edge-triggered flip-flop in the situation where there are two chained flip-flops (that is, the output of the first one serves as input to the second one). When clock rises, the input to the first flip-flop gets sampled and propagates to the second flip-flop. Then, after one clock period, when clock rises again, the second flip-flop samples its input. But the input of the second flip-flop must remain at the same value for at least a hold time after the clock rises, if we want it to get correctly stored. So, the first flip-flop must guarantee that its output (which is the input for the second flip-flop) will not change for at least a hold time. That is, the contamination delay of the first flip-flop must be at least the hold time of the second flip-flop.

Is this correct? The part that I'm not understanding is why this fact gives to registers "the important property that its inputs and outputs can be read and written simultaneously (that is, by similar devices sharing the same clock input)".

From my textbook, Digital Design and Computer Architecture, Harris and Harris, pg. 88

An important note

When you are attempting to find the propagation delay of a combinational circuit with multiple elements, you must add the propagation delay through the critical path.

However when you are attempting to find the contamination delay of a combinational circuit with multiple elements, you must add the contamination delay through the shortest path.

That much is probably obvious to you.

Actually, it sounds to me like you are referring to contamination delay. You said contamination delay is the amount of time measured after an input changes that the output remains valid. If you mean the previous output, then yes, because that means the same thing as until the output begins changing to the new value.