Electronic – How do i read the RGB values of an image in Verilog from a hex file generated in Matlab for processing

Use Yosys, the free and open source awesomeness HDL Synthesis Toolbox with extra doses of being cool (and free) (and faster than current-gen Vivado) (did I mention Free as in speech & beer?) (and awesome)!

Get yosys, and the xdot utility (often part of a package called python-xdot) as well as graphviz.

Then, do something like in a verilog file (let's call that minifsm.v):

module piggybank (
                  input         clk,
                  input         reset,
                  input [8:0]   deposit,
                  input [8:0]   withdrawal,
                  output [16:0] balance,
                  output        success
                  );
   reg [16:0]                   _balance;
   assign balance = _balance;
   wire [8:0]                   interest = _balance [16:9];
   reg [5:0]                    time_o_clock;
   localparam STATE_OPEN = 0;
   localparam STATE_CLOSED = 1;
   reg                          openness;
   assign success = (deposit == 0 && withdrawal == 0) || (openness == STATE_OPEN && (withdrawal <= _balance));
   always @(posedge clk)
     if(reset) begin
        _balance <= 0;
        openness <= STATE_CLOSED;
        time_o_clock <= 0;
     end else begin
        if (openness == STATE_CLOSED) begin
           if(time_o_clock == 5'd7) begin
              openness <= STATE_OPEN;
              time_o_clock <= 0;
           end else begin
              time_o_clock <= time_o_clock + 1;
           end
           if (time_o_clock == 0) begin //add interest at closing
              _balance <= _balance + interest;
           end;
        end else begin //We're open!
           if(time_o_clock == 5'd9) begin // open for 9h
              openness <= STATE_CLOSED;
              time_o_clock <= 0;
           end else begin
              _balance <= (success) ? _balance + deposit - withdrawal : _balance;
              time_o_clock <= time_o_clock + 1;
           end
        end // else: !if(openness == STATE_CLOSED)
     end // else: !if(reset)
endmodule // piggybank

and run yosys:

yosys

 /----------------------------------------------------------------------------\
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 |  yosys -- Yosys Open SYnthesis Suite                                       |
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 |  Copyright (C) 2012 - 2016  Clifford Wolf <clifford@clifford.at>           |
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 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
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 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
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 |                                                                            |
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 Yosys 0.6+155 (git sha1 a72fb85, clang 3.7.0 -fPIC -Os)

load the verilog file, then check the hierarchy, then extract the processes, optimize, find the state machines, optimize, and show a graph:

yosys> read_verilog minifsm.v
… …
yosys> hierarchy -check;
yosys> proc;
yosys> opt;
yosys> fsm;
yosys> opt;
yosys> show;

and you'll get something like

With different options to the show command you can also just save the graph to a file. Yosys allows you to write "flattened" logic in verilog, EDIF, BLIF, …, synthesize and map for specific technological platforms, including these supported by ArachnePnR, and do much more interesting things. In essence, Yosys is like letting someone who knows how to build compilers write a verilog synthesizer.

In this case, it might be a good idea to preprocess the image into an intermediate format with a different programming language that actually has image manipulation libraries, such as Python with PIL. You really don't want to have to deal with parsing the MIF format in Verilog. Once you've read in the image, then you can write out a 160x120 array in a format that you can read in easily in Verilog.