Electronic – How is a VHDL variable synthesized by synthesis tools

rtlsynthesisvhdl

I know two ways in which a VHDL variable is synthesized by synthesis tool:

Variable synthesized as Combinational logic
Variable synthesized as a Latch unintentionally (when an uninitialized variable is assigned to a signal or another variable)

What are the other ways in which a VHDL variable can be synthesized ? (Example: can it be interpreted as a FF ? )

Best Answer

I would distinguish three possibilities:

A VHDL variable has no hardware representation at all. Assume the following example
```
signal a,b,c : integer;  
...  
process ( clk ) is  
variable var : integer := 0;  
begin  
if ( rising_edge(clk) ) then  
var := a + b;  
c <= var;  
end if;  
end process;
```
The variable var is not really synthesized as combinatorial logic at all (assuming this is what was meant in the question). It's rather the right hand side of the assignment a + b that is synthesized into hardware. Strictly speaking a variable never is synthesized into combinatorial logic.
A variable merely holds an intermediate result, which is either evaluated in the same clock cycle -> no hardware synthesized ( this is 1) again ), or is evaluated in the following clock cycle -> a flipflop is synthezised.
One of those dreaded latches is inferred in such cases where conditional branches exist in which the variable is assigned neither a new value (depending on some signals) nor a default value. Usually this case happens unintended :-)

Related Solutions

Electronic – Which synthesis tools support VHDL libraries

I use the following tools which all have full library support:

Riviera-PRO (from at least version 2006.02 onwards)
Xilinx ISE (from at least version 10 onwards)
Quartus (from at least version 10.0 onwards; Two or more entities with the same name cannot be used, however, only packages)
Synplify (from at least version 9.0 onwards)

The only caveat is that the XST tool in the Xilinx toolchain is incapable of performing automatic file ordering on projects where entity names exist in multiple libraries (it ungraciously gets stuck looping forever trying to resolve dependencies).

Electronic – How to avoid latches during synthesis

To avoid latches, you need to make sure all of your outputs are assigned at all possible branches of the code.

for example,

if a = '1' then
   b(0) <= '1';
else
   b(1 downto 0) <= "00";
end if;

would generate a latch, because in the first condition, the value of b(1) is not specified, so the compiler decided you wanted to keep the previous value of b(1) there. One way to write this that would not generate a latch is:

if a = '1' then
   b <= prev_b;
   b(0) <= '1';
else
   b(1 downto 0) <= "00";
end if;

...

if rising_edge (clk)
    prev_b <= b;
end if;

Here you explicitly state that b should retain it's old value, and then overwrite b(0) with the new value.

Another way is to give b a default value, as in @TomiJ's answer.

If you post the code you are getting a latch on, we could help you find the specific reason.

Best Answer

Related Solutions

Electronic – Which synthesis tools support VHDL libraries

Electronic – How to avoid latches during synthesis

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