Verilog – How to Declare Register Values as Input in Verilog

verilog

I have a data set consisting of 30 values and each of 16 bit wide. I tried to add these values as an input in my Verilog code in the following way:

`timescale 1ns / 1ps
module com (inp,clk,out);
input clk;
input reg [15:0] inp;//dataset
output out;
.
.
.

but when I am writing input reg [15:0] inp; it is showing some error.

Can anybody tell me how can I use this data set values as an input in my verilog code.

Best Answer

If you want to assign a value to something, then it is a register (reg). If you want to connect two things, then you need a wire. If you want to get a signal from an external block you use an input and if you want to send a signal to an external block you use an output. outputs can be wires or regs, but an input cannot be a reg. If you're trying to assign a value to inp inside your block, then how can you also say the value of inp is determined by another block?

Maybe this is more what you're trying to do: on the clock edge, if reset is high then inp_registered gets 0. Otherwise, it gets the value of inp:

module com(
    rst,
    clk,
    inp
);

input rst;
input clk;
input [15:0] inp;

reg [15:0] inp_registered;

[...]

always @(posedge clk) begin
    if (rst == 1) begin
        inp_registered = 0;
    end
    else begin
        inp_registered = inp;
    end
end
endmodule

Related Solutions

Electronic – Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

(Disclaimer: I'm not a Verilogger - its signed arithmetic foibles being one of the reasons why not :)

Prior to Verilog-2001 all vector arithmetic in Verilog was unsigned.

In Verilog-2001 you can explicitly call for signed arithmetic, so I think you'll need to cast your in:

if ($signed(in) < 0)
 out = -$signed(in);
else
 out = in;

Reading matter which may be of interest:

Signed arithmetic in Verilog-2001 - Opportunities and Hazards

Electronic – “is not declared” error in Verilog

You need to give the instance a name (see below)

It also looks like you may be trying to declare it in an always block, this won't work. Declare it outside any blocks (e.g. at the top of the module)

Also, using the "connection by name" (or named association) method of instantiation rather than "connection by order" (or positional association) is less prone to accidental errors from getting the order wrong, especially with modules with many ports.

So the instantiation for connection by name would be

encoder8to3 enc_instance (.A(LL), .B(x), .F(FAULT));

With this method it could be written like this and still be correctly connected:

encoder8to3 enc_instance (.A(LL), .F(FAULT), .B(x));

Whereas using:

encoder8to3 enc_instance (LL, FAULT, x);

would connect B to FAULT and F to x.

Here's a reasonable pdf on modules and instantiating them. I agree good Verilog tutorials are quite thin on the ground (compared to something like C) so starting out can be a bit bewildering.
If you can find a copy at a reasonable price, I do highly recommend the Pong Chu book "FPGA Prototyping with Verilog Examples" I mentioned in my answer to your other question, as well as the focus on synthesis I mentioned, it goes through everything you need to start writing decent code, and is very clear and concise.
There is also a google mailing list for Verilog you might find of use, and fpga4fun has some good tutorials and a forum. And of course there is here :-)

EDIT - about where to declare the module:

The instantiation only connects the ports together, so where you declare it (outside a block) doesn't matter.
If you want to do something with this module inside the always block use some intermediate logic. Create a couple of registers, use the always block to manipulate them as desired, then tie these to the instantiated module ports (in the instantiation).

The way you have it at the moment, the instantiated module can be seen as in parallel with your module rather than inside it, as it just connects directly to the inputs and output of the module. Have a look at the RTL schematic to see what is being generated by the code (under synthesis in the design tab)

Best Answer

Related Solutions

Electronic – Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

Electronic – “is not declared” error in Verilog

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