In the reference designs for a few FPGA development boards, I have observed that, there is always a PLL which generates two clocks at the same frequency but not in phase. One clock feeds to the SDRAM controller while the other "delayed" feeds the SDRAM_CLK which is output from the FPGA. I only know that the delayed clock is required since there is propagation delay between the FPGA and the SDRAM and the communication will not be synchronized between the two devices if this phase shifted does not exist. Is this the reason?
What is supposed to be the relationship between these two clocks and how does one determine how much phase difference is required for correct operation?
Best Answer
This is most likely related to meta stability. The output of the controller needs to be stable for the hold time. Otherwise you can have a situation as shown in the figure below.
If your signal from the controller (A) is not stable for long enough before the memory clock (C2), the latched signal at the memory (B) can be meta stable. It can be high, low, or a voltage between high and low. The behavior is undefined.
To determine the delay required you need to complete the timing closure analysis with the memory (SDRAM) timing constraints using your tool chain.