Electronic – How to find Gate Delay

delaydigital-logic

I need to find the delay of a full adder. I searched for it but I couldnt find absolute information.

Sample delays : XOR – 8ns / AND – 2ns / OR – 2ns
enter image description here

What is the delay of this circuit?

My Solution

I think the delay is the maximum time.
For Full Adder : XOR + XOR = 16ns (max) Is it correct?
Another question is how can I find the delay of 4-bit adder?

Thanks in advance.

Best Answer

For a single-bit adder, the worst-case propagation delay is the longest time it will take to get a stable output, which for this case is 16ns.

schematic

simulate this circuit – Schematic created using CircuitLab

However, for an N-bit adder, you should consider the path from the input's least significant bit (LSB) to a stable output's most significant bit (MSB)-- $$A_0 \rightarrow C_{out,0} \rightarrow C_{out,1} \rightarrow C_{out,2} \rightarrow S_3 (1)$$ (Cin, i is implied, but not shown).

In the case of your circuit, we're given the following paths $$A_i \rightarrow S_i = 16ns (2)$$ $$A_i \rightarrow C_{out,i} = 12ns (3)$$ $$C_{in,i} \rightarrow S_i = 8ns (4)$$ $$C_{in,i} \rightarrow C_{out,i} = 4ns (5)$$

From this, we calculate the longest path previously shown in (1). This calculates to be $$12ns + 8ns + 8ns + 8ns = 36ns$$

For more information, please refer to this lecture on adder circuits