Electronic – How to find MAX V CPLD pinout

Altera provides source code for something they call a Jam STAPL player. If you build it with an I/O implementation that is slower than intended, it will work but program things more slowly.

As @Claudio states, the I/O pins will all be high-z during configuration.

In terms of reset, during configuration, all of the registers should be initialised to whatever default value was specified when the design was synthesized.

However I would not rely on this as your only source of reset. When you first power on the device, the state of any clock source or input source that you are using cannot be guaranteed - the clock for example may be an oscillator with some start-up time during which it may be unstable. As a result you may end up with weird metastability issues if your design has no other reset source.

If you do not have any external reset, the simplest solution would be a basic reset synchroniser chain of a few registers. The registers would be initialised to zero, and the input to the first would be a logic 1. This means that the output of the chain would hold everything in reset for a few clock cycles (as many as in the chain) after power on giving time for external I/O connections to settle down.

I would still however consider your design to see if there are any conditions - e.g. errors in control/data paths - that you consider to be fatal and use that as a secondary source to reset the system if something goes terribly wrong.