Electronic – How to generate sound in VHDL

audiofpgasoundvhdlwaveform

I'm new to FPGA and VHDL. I'm working on lab practical and for the practical we were already given file that has an I2C codec and the basics for the codec registers were already done but I found the given files were too complicated and I couldn't understand it; they were things like slave and masters. So I decided to follow an online tutorial.

I am using a DE0-Nano board. I want to make three different waves (sound) so I followed an online tutorial to make sine wave, but when I tested it on my board nothing happened, and I didn't get any sound. Is there something missing on my code or did I assign to the wrong pins?
Here is the documentation for the board just in case you need it.

I would also appreciate if you can also tell me about any source that will help me understand I2C and the slave/master.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;   
entity sinewave is
port (
      clk :in  std_logic; -- I tried connecting it to PIN_B14 & PIN_R8
      dataout : out integer range -128 to 127 -- connect to PIN_A9
      );
end sinewave;

architecture Audio of sinewave is
  signal i : integer range 0 to 30:=0;
  type memory_type is array (0 to 29) of integer range -128 to 127; 
  signal sine : memory_type := (0,16,31,45,58,67,74,77,77,74,67,58,45,31,16,0,
-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16);

begin

process(clk)
begin
  if(rising_edge(clk)) then     
    dataout <= sine(i);
    i <= i+ 1;
    if(i = 29) then
      i <= 0;
    end if;
  end if;
end process;

end Audio;

Best Answer

You've got a whole lot of things mixed up:

First off, the DE0 Nano has an ADC, not a DAC. It converts analog voltages to digital values, not the other way around.
You can't write an integer to a single pin, it doesn't make any sense. A GPIO pin can be either a zero or a one. To output a parallel signal, you need to declare a std_logic_vector and assign a set of pins.
R8 is the input of a 50MHz clock. You'll probably want to divide that down quite a bit before you try to generate an audio frequency sine wave.
Even if the ADC was actually a DAC (it's not), you can't simply assign numbers to the pins it's connected to. You need to read the datasheet to understand how to communicate with a device. For the ADC, here's the datasheet, note that it communicates via a serial data stream (compatible with SPI).
I2C and audio don't really mix. You might be thinking of I2S, which is digital, serial, often multichannel, audio. I2C is typically too slow/not appropriate for audio. If you want to learn more about I2C, the Wikipedia page is pretty straightforward. If you want to learn about I2S, read up on I2S, and then get yourself an I2S DAC.

So, with all this in mind: if you want to output audio, instead of trying to use the non-existent DAC on the DE0 Nano, use PWM to output an analog voltage. You can use a PLL to get a high-frequency PWM frequency so that it can be very easily filtered (simple RC LPF) to get a passable audio signal.

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Electrical – Select output from Generate in VHDL

You can describe it using a high-impedance output of your RAM. All RAMs, which are de-selected, output all 'Z' on the data signal. Only the selected RAM actually outputs the requested value. Then, the outputs of all RAMs can be connected together without creating a short-circuit. That means, all RAMs "write" to the same signal. Some tools can even synthesize it, by replacing the 3-state driver by appropriate logic gates of the target architecture if required (e.g. ISE 14.7).

Example design:

library ieee;
use ieee.std_logic_1164.all;

entity RAM is
  generic (
    CONTENT : std_logic_vector(7 downto 0));

  port (
    read_enable : in  std_logic;
    read_data   : out std_logic_vector(7 downto 0));
end entity RAM;

architecture rtl of RAM is
begin
  read_data <= CONTENT when read_enable = '1' else (others => 'Z');
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
  generic (
    N : positive);          -- number of RAMs

  port (
    read_enable : in  std_logic_vector(N-1 downto 0);
    read_data   : out std_logic_vector(7 downto 0));
end entity top;

architecture rtl of top is

begin  -- architecture rtl

  gRAMs: for i in 0 to N-1 generate
    RAM_inst: entity work.RAM
      generic map (
        CONTENT => std_logic_vector(to_unsigned(i, 8)))
      port map (
        read_enable => read_enable(i),
        read_data   => read_data);
  end generate gRAMs;

end architecture rtl;

If you simulate it using this testbench:

library ieee;
use ieee.std_logic_1164.all;

entity top_tb is
end entity top_tb;

architecture sim of top_tb is
  constant N : positive := 4;
  signal read_enable : std_logic_vector(N-1 downto 0) := (others => '0');
  signal read_data   : std_logic_vector(7 downto 0);

begin  -- architecture sim
  DUT: entity work.top
    generic map (
      N => N)
    port map (
      read_enable => read_enable,
      read_data   => read_data);

  Stimuli: process
  begin
    wait for 10 ns;
    for i in 0 to N-1 loop
      read_enable(i) <= '1';
      wait for 10 ns;
      read_enable(i) <= '0';
    end loop;
    wait;
  end process;
end architecture sim;

then you get the following result:

Best Answer

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