I searched a technology document about placement of decoupling capacitors and the main idea is shown in the following picture:
I think it is reasonable but do I have to put the decoupling capacitor and MCU in the same layer? it is not convenient for me to place other devices. So i choose to place the decoupling capacitor in the bottom layer
My PCB is a four-layer(signal-power-gnd-signal) one and when I split power and gnd layers the two vias closing to the pins of MCU in the above picture will not be included in net of power and gnd layer. Does it have the same nice performance as the case f in picture one? Do i have to take of inductance of vias in this case?