I think you're on the right path, a couple of notes,
1) With a signal trace between two planes, the return current will split between the two planes, even if one of the planes is split. The return current cannot "see the future" and decide ahead of time which plane to return on. It will return above and below the trace until it sees the split at which point is says "oh crap!" and pays you back by possibly causing you to fail FCC testing. So you want to avoid running traces over plane splits even if another adjacent plane is not split. You can deal with splits with capacitors and such but this type of solution is less than ideal. I'd focus on always avoiding running a trace over a plane split on an adjacent plane.
2) Wide return paths on DC signals don't really matter.
3) You asked about two signal layers sharing the same plane. Usually, this is not a big deal if done properly. What many people do is use one of the layers as a "horizontal" signal layer and the other as a "vertical" signal layer so the return currents are orthogonal to each other. It is very common to route two signal layers for each plane, and use this horizontal/vertical technique. The most important thing to remember is to not change reference planes. Your setup could be a little tricky because going from the bottom layer to the 4th layer adds another return plane. More typical 6 layer boards are
1)ASignalHor 2)GND 3)ASignalVer 4)BSignalHor 5)POWER 6)BSignalVer
If you need smaller additional planes, like under the micro, these would usually be placed as an island on one of the signal layers. If you need to use more power planes, you might want to think about going to 10+ layers.
4) Plane spacing is important, and can have huge impact on performance, so you should specify this to the board house. If you take the example 6 layer stackup I mentioned above, spacing of .005 .005 .040 .005 .005 (instead of standard stackup with equal distance between layers) can make an order of magnitude improvement. It keeps the signal layers close to their reference plane (smaller loops).
The quick answer:
Any signal that crosses a split in the power OR ground plane is bad. The higher the switching rate (and the faster the signal edges are), the worse the effects will be.
The long answer:
When you say, "I will provide a solid current return path on the ground plane (bridge between digital and analog) so return currents shouldn't be an issue", either you don't understand the issues, or I didn't understand your statement. The reason that I say this is that you can't have a "solid current return path" and still have a split plane. There has to be some non-solid-ness in there.
The return currents will flow on the closest power OR ground plane to the signal. So in your case, if your signal is on the the top layer then the return currents will be on your ground layer. But if your signal is on the bottom layer then the return currents will be on the power layer. For most medium to high speed signals, the return current will follow the signal trace, and not take the shortest path. To put it another way, the return currents will try to minimize the "loop area".
If your signal switches from the bottom to top (or vise versa) then the return currents will also switch, flowing through a decoupling cap. This is why it is important to sprinkle decoupling caps all over the PCB, even when it's too far away from a chip to make any difference on power.
Minimizing the loop area is critical for signal integrity, minimizing EMI, and reducing the effects of ESD.
If your signal cuts across a split in the power/ground plane then the return currents are forced to take a detour. In some cases, this detour can increase the loop area by 2x or even 10x! The most simple and best way to avoid this is to not run a signal across a split.
Some boards have mixed analog and digital planes, or on some systems have multiple power rails. Here's a list of things that might help out in these circumstances:
For things like clocks or active data lines, you really don't want to cross a split. Some creative PCB routing is the best solution, although sometimes you just have to have a combined analog/digital plane instead of splitting it.
For low-speed signals, or signals that are mostly DC, you can cross a split but be careful and selective about it. If you can, slow down the edge rate using a resistor and maybe a cap. Usually the resistor would be physically bridging the split.
Things like 0-ohm resistors, or caps, can be used to provide for a signal return path between two planes. For example, if a signal does jump the split, adding a cap between the two planes near the signal can help. But beware, if this is not done well then it could negate any positive effects of having a split in the first place (I.E., keeping the digital noise from going to the analog plane). The nice thing about using caps or 0-ohm resistors for this is that it allows you to play around with the design after the PCB has been made. You can always stuff or unstuff parts to see what happens.
While many PCB designs will involve some sort of compromise, try not to compromise unless you absolutely have to. You'll have less headaches, and loose less hair, by doing that.
I should also point out that I completely glossed over the issue of impedance changes due to the split, and what that would mean. While important, it's not as important as minimizing the loop area and stuff. And understanding the loop area is much easier than understanding how the impedance changes will effect the signal integrity.
Best Answer
It is not unusual to run the same track over multiple layers to produce a high-current track. I have done this to route 100 A across a PCB.
The I2C signals do not have sharp edges and so the maximum track frequency will be relatively low. They should be fine.