Electronic – In VHDL 2008, can a type from a package with generics be used for a port signal

So I can define a package with a generic – in this case, the package takes a size as a generic and defines a vector type of that size:

library ieee;
use ieee.std_logic_1164.all;

package vector_package is
    generic (
        size : integer);

    subtype vector_t is std_logic_vector (size - 1 downto 0);
end package;

Now I can instantiate that package within an architecture to create a signal of that vector type:

entity foo is
end entity;

architecture rtl of foo is
    package vp_4 is new work.vector_package generic map (size => 4);
    signal vector : vp_4.vector_t;
begin
end architecture;

But what I want is to use the vector type for a port signal. I would have expected to be able to do something like this, but it does not appear to be valid VHDL 2008:

package vp_4 is new work.vector_package generic map (size => 4);

entity bar is
    port (
        signal vector : out vp_4.vector_t);
end entity;

This is rejected by ModelSim 10.2c with the message (vcom-1136) Unknown identifier "vp_4". in the line containing signal vector : ....

Is there a way to use the type from the package for a port signal? I am aware of unconstrained types as an alternative, but they do not fit my requirements in the actual use case.