The basic difference is a gating or clocking mechanism. For example, let us talk about SR latch and SR flip-flops.
An SR Latch will look like this
In this circuit when you Set S as active the output Q would be high and Q' will be low. This is irrespective of anything else. (This is an active low circuit so active here means low, but for an active high circuit active would mean high)
An SR Flip-Flop (also called gated or clocked SR latch) looks like this.
In this circuit the output is changed (i.e. the stored data is changed) only when you give a active clock signal. Otherwise, even if the S or R is active the data will not change. This mechanism is used to synchronize circuits and registers so that the data does not change unnecessarily.
A D flip flop simply latches the value of a wire on it's D pin at the rising edge of a clock. Using three inputs (S, R, and Q (output of the DFF)), you need to create a small combinational circuit which mimics an SR flop:
If S is set, the value of D should be 1
If R is set, the value of D should be 0
If neither is set, the value of D should be Q
With these three statements it's simple to create a small truth table and from that to create the combinational circuit which should drive your D pin.