Electronic – Large SiGe ASICs for digital logic

To answer your question, the same guidelines do not apply to ASICs and gated clocks are used very often to reduce power consumption.

In FPGAs, clock signals have dedicated routing resources that ensure low skew delivery of the clocks to fairly large areas of circuitry. If you try to gate the clock then the output of the gate will probably be forced to use normal logic signal routing resources, which can introduce significant delays and cause large clock skews. FPGAs are designed with some assumptions about how logic design should be done, and one of those assumptions is that you use clock enable signals rather than gated clocks. For common FPGAs the power consumption is enormous anyway so there is little motivation to gate the clocks.

ASICs are a much different beast. When you design an ASIC you have complete control over the gates and wires. You can safely create a gated clock and make sure that the gated clock signal is distributed properly. This is a very common technique for minimizing power consumption. For example, look at a modern microcontroller and you will see that you can, in software, turn the clock signal on and off for large chunks of circuitry such as a UART. The downside is that ASIC designers must use very expensive and sophisticated timing analysis tools to get this right.

SiGe is a semiconductor alloy, meaning a mixture of two elements, silicon and germanium. Since 2000 or so, SiGe has become widely used to enhance the performance of ICs of various types. SiGe can be processed on equipment nearly the same as used for ordinary silicon. SiGe doesn't have some of the drawbacks of III-V compound semiconductors like gallium arsenide (GaAs), for example it doesn't lack a native oxide (important for forming MOS structures) and doesn't suffer from mechanical fragility that limits the wafer size of GaAs. This results in costs that are only a small multiple of ordinary silicon, and so much lower than competing technologies like GaAs.

SiGe allows two main improvements compared to ordinary silicon:

First, adding germanium increases the lattice constant of the alloy. If a layer of Si is grown on top of SiGe, there will be mechanical strain induced by the lattice constant mismatch. The strained layer will have higher carrier mobility than unstrained Si. This can be used, for example, to balance the performance of PMOS and NMOS transistors, reducing the area needed for a given CMOS circuit.

Second, the SiGe alloy can be used selectively in the base region of a BJT to form a heterojunction bipolar transistor (HBT). SiGe HBT's have been demonstrated with speeds (f_T) to 500 GHz, and are commercially available with f_T up to 240 GHz. The SiGe HBT also has lower noise than a standard silicon BJT.