circuit analysisdigital-logic
I understand logic gates and their truth tables. However, when it comes to the circuits of the gates, I have trouble understanding them. Could someone please explain how a gate such as the following can be compared to the NAND logic gate?
(original image source Basic Logic Gates and Buffers)
You can build the mux with 4 NOR gates, too. It doesn't require extra inverters on the inputs and outputs, if that's what you were doing. Note that the sense of the "select" input is inverted, so you need to swap the "A" and "B" inputs to compensate.
I think this is a solution, after playing with the expression a bit.
simulate this circuit – Schematic created using CircuitLab
Derivation:
$$ AB\overline{C} + A\overline{B}C + \overline{A}BC + ABC$$ $$ = AB(C+\overline{C}) + A\overline{B}C + \overline{A}BC $$ $$ = AB + A\overline{B}C + \overline{A}BC $$ $$ = AB + C\cdot(A\overline{B} + \overline{A}B) $$ $$ = \overline{\overline{AB} \cdot \overline{C\cdot (A\overline{B} + \overline{A}B)}} $$ $$ = \overline{\overline{AB} \cdot \overline{C\cdot (A+B)\cdot\overline{AB}}} $$ Turning the 3-input NAND into 2 2-input NANDs and an inverter: $$ = \overline{\overline{AB} \cdot \overline{C\cdot \overline{\overline{(A+B)\cdot\overline{AB}}}}} $$
Best Answer
The best way to do this is to analyze each case separately. This gate has two input signals, so only four combinations to analyze. For each case write down the inputs and the resulting output. After the four cases, you have a truth table, which you say you already understand.
Here is the case with both inputs 0:
Both transistors are obviously off, so the pullup drives the output high.
Now do the (1,0) inputs case:
The bottom transistor is obviously off, so again the outut can only be high.
Case (0,1):
Case (1,1):
From these four cases you get the truth table:
In1 In2 Out --- --- --- 0 0 1 1 0 1 0 1 1 1 1 0which is the NAND function.