Electronic – Low voltage GPU decoupling capacitor longevity

Large decoupling capacitors such as those are meant to compensate for larger sags in the supply of the chip. Using a larger value will not hurt.

Don't skimp out on the smaller value decoupling capacitor though, since it's used to filter high-frequency noise from/on the supply; use as close to the prescribed value as possible, otherwise use a 100nF.

General-purpose decoupling caps are rarely engineered to precise tolerances. In most cases, there's a huge range of values (generally many orders of magnitude) that will work, although those near the extremes aren't as good as those nearer the middle. For example, a 3.3 volt chip might malfunction if the voltage dips by 0.5 volts or more, but work correctly if it dips by 0.49 volts or less; from the chip's perspective, a bypass cap that allows VDD to briefly dip 0.4 volts would be adequate, but any "high" outputs would dip by 0.4 volts any time VDD does. That might not make attached devices malfunction, but could increase the amount of radiated interference or make the device more susceptible to radiated interference that arrives just at the moment of a dip. Since such dips on VDD are ugly, and it's often difficult to guarantee when they will or will not be problematic, designers generally try to use sufficient bypass caps to keep VDD dips below 100mv or so.

Consequently, if one were to place a bunch of chips on their sides radially around a bypass cap, one could probably achieve acceptable electrical bypassing using one cap for a dozen or so chips (figuring that every chip would be within 0.1" or so of the cap). From a practical perspective, however, trying to have a dozen chips that close to a single bypass cap would be a manufacturing nightmare. What is required is not that one have a bypass cap for every chip, but rather that each chip power input have a very short direct connection to a bypass cap; achieving that is generally easiest if each chip has its own bypass cap, but if the layout allows two chips to have good bypass connections to a single cap, and both chips are comparably sensitive to VDD noise, sharing a bypass cap is generally just fine.

Incidentally, another thing to consider with bypass caps is the consequence of not having them: if a chip doesn't have a bypass cap, one should assume that its internal state will be scrambled and combinatorial outputs may randomly glitched briefly when any input changes. If the a chip has no internal state that one cares about, and is used in such a fashion that one wouldn't care if the outputs glitched in response to input changes (e.g. its inputs all change synchronously with a common clock signal, and the outputs won't be sampled until some time later), one may be able to omit that chip's bypassing altogether. Proper bypassing would likely reduce electromagnetic interference, but from an operational standpoint it wouldn't affect anything.