I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain crossing boundaries, but my confusion is that the output of metastability is unpredictable, it might lead to high or low level, and that output then will be propagated to the rest of the circuit, so how can the second or the third flip flop catch the right value to be transmitted , if the first flip flop is always at metastable state and might settle in a wrong level ?
Electronic – Metastability error propagation with flip flop
cdcflipflopmetastabilitysynchronization
Related Solutions
When a flip-flop is metastable it doesn't oscillate. It just gets stuck at an indeterminate level between Vhi and Vlow.
When it finally drops out of the metastable state it could go to either the high or low state.
It's not obvious what you mean by "settle to the input value". Normally you get in to a metastable state by having an input value that is in the middle of a transition when the clock arrives. It's not at either a legal high or low value. So when you say the "input value" neither I nor the flip-flop knows whether you mean the value prior to the transistion or after the transition.
Edit:
Here is a scope trace showing the output of a flip-flop going through a metastable state, with the exit from the metastable state taking a random amount of time:
Picture taken from W. J. Dally, Lecture notes for EE108A, Lecture 13: Metastability and Synchronization Failure (ow When Good Flip-Flops go Bad) 11/9/2005.
Provocative question: have you tried googling for Flip-flop D counter? I found this.
The trick is that if you feed back the inverted output of the flip flop to the input, you get a circuit that divides the clock frequency by two.
The principle is not that hard to grasp. The flip flop D replicates the D input to the output Q when the clock rises. The inverted output is the opposite: if you connect it to the input, at every clock cycle the input will get inverted, and thus the output. This happens at every rising edge, so every two clock edges (rising and falling) you have one output edge (rising or falling).
Cascading three flip flops and taking their outputs as the three bits of the value, you get a base-8 counter. You can see that from the truth table: Q0 changes at every count, Q1 every two and so forth.
It's hard (impossible?) to describe the behavior with just truth tables, but basically D0=Q0', D1=Q1' and D2=Q2'. Then, CLK1=Q0 and CLK2=Q1.
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Best Answer
The first FF is not always metastable. Assuming that input edges are uniformly distributed with respect to its clock, the first FF has a certain probability of going metastable that is related to the clock period and its setup/hold time requirements. If it does go metastable, it resolves itself within some amount of time — the probability of remaining metastable after time t is an exponentially decaying function of t.
The second FF has a much lower probability of going metastable, because it would have to get clocked at just the right instant when then first FF (if it was metastable) happened to be resolving itself. Otherwise, its output will be either definitely high or definitely low. The signal change might be delayed by an extended metastability of the first FF, but it is very unlikely to cause the second FF to go metastable and adversely affect the operation of the rest of the logic.
A third FF reduces the chances of metastability to infinitesimal levels.