Electronic – Minimal redistributable coregen output for command-line rebuilds

fpgaiselicensingverilogxilinx

I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but coregen's output doesn't appear to be redistributable (the resulting verilog source claims to be confidential and proprietary information of Xilinx, who reserves all rights and doesn't specifically grant the right to redistribute AFAICT).

Is there a command-line/Makefile recipe somewhere for getting similar output from coregen that I can redistribute to my users?

http://github.com/atgreen/moxie-cores , btw.

Best Answer

The coregen GUI will produce a file ending in .xco that appears to be redistributable. This file contains commands to feed coregen in batch mode (coregen -b FOO.xco -p PROJ.cgp)

Related Solutions

Electronic – Using Webpack from the command line, but without a project file

Not that I am aware. Another approach is to use a script instead of a makefile. The script can then create the project file so you do not to manually edit multiple files.

You can use TCL to drive the ISE tools. The ISE tools will generate example code for you. More information on using TCL can be found here, http://devbisme.webfactional.com/blogs/devbisme/2012/04/03/running-weeds

If you want a Python option for building Xilinx ISE projects, see Guenter Dannoritzer's Python scripts, which generate the underling tcl, but the OO interface in Python is better than generating tcl directly, http://www.myhdl.org/doku.php/projects:ise_py. I have made some updates to the scripts here, https://bitbucket.org/cfelton/examples/src/tip/tools

An example, you can quickly and as easily create an ISE project.

# set up pin configuration for the FPGA
fpga = Fpga(path=ppath)
fpga.setPin('clk', 'P124')
fpga.setPin('srst', 'P8')
fpga.setPin('led<0>', 'P92')
fpga.setPin('led<1>', 'P93')
fpga.setPin('led<2>', 'P95')
fpga.setPin('led<3>', 'P96')
fpga.setPin('led<4>', 'P97')
fpga.setPin('led<5>', 'P98')
fpga.setPin('led<6>', 'P99')
fpga.setPin('led<7>', 'P100')
fpga.setDevice('spartan3', 'xc3s400', 'tq144', '-5')

imp = Xilinx(ppath, 'stroby')

imp.setFpga(fpga)
imp.addHdl((vfile))
imp.createTcl() 
imp.run()

Electronic – Generating a MSS file at command-line

You can use the Xilinx tool appguru to generate an MSS file from the exported XML file

appguru -hw proc.xml -app empty_application

See appguru -h for help

Best Answer

Related Solutions

Electronic – Using Webpack from the command line, but without a project file

Electronic – Generating a MSS file at command-line

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