Electrical – How to generate .xst file from command line + Xilinx-ISE

fpgaxilinx

I am trying to learn how to generate bit files from command line. Is there a way to generate the .xst script file from command line tools? I can only find mention of it being something that the GUI auto-generates.

To add some context, I build and generate a bit file for a simple design in the GUI then use the 'View Command Line Log' tool to generate the commands the tool used. Then use "Cleanup Project Files". I am just trying to execute the same commands manually from the command line. The first command is:

xst -ifn "C:/Users/Documents/XilinxProjects/SingleItemTest/item.xst" -ofn "C:/Users/Documents/XilinxProjects/SingleItemTest/item.syr"

Which gives me:

ERROR:Xst:427 - Entry File C:/Users/Documents/XilinxProjects/SingleItemTest/item.xst not found

Best Answer

Our PoC-Library can run Xilinx XST from command line via Python3. We are using template files for XST, because each target device can have other XST options.

Here is a *.xst file for a 7-Series XST run:

set -xsthdpdir "xst"
run
-ifn {prjFile}
-use_new_parser {UseNewParser}
-ifmt {InputFormat}
-ofn {OutputName}
-ofmt {OutputFormat}
-p {Part}
-top {TopModuleName}
-opt_mode {OptimizationMode}
-opt_level {OptimizationLevel}
-power {PowerReduction}
-iuc {IgnoreSynthesisConstraintsFile}
-uc {SynthesisConstraintsFile}
-keep_hierarchy {KeepHierarchy}
-netlist_hierarchy {NetListHierarchy}
-rtlview {GenerateRTLView}
-glob_opt {GlobalOptimization}
-read_cores {ReadCores}
-sd {SearchDirectories}
-write_timing_constraints {WriteTimingConstraints}
-cross_clock_analysis {CrossClockAnalysis}
-hierarchy_separator {HierarchySeparator}
-bus_delimiter {BusDelimiter}
-case {Case}
-slice_utilization_ratio {SliceUtilizationRatio}
-bram_utilization_ratio {BRAMUtilizationRatio}
-dsp_utilization_ratio {DSPUtilizationRatio}
-lc {LUTCombining}
-reduce_control_sets {ReduceControlSets}
-fsm_extract {FSMExtract}
-fsm_encoding {FSMEncoding}
-safe_implementation {FSMSafeImplementation}
-fsm_style {FSMStyle}
-ram_extract {RAMExtract}
-ram_style {RAMStyle}
-rom_extract {ROMExtract}
-shreg_extract {ShRegExtract}
-rom_style {ROMStyle}
-auto_bram_packing {AutoBRAMPacking}
-resource_sharing {ResourceSharing}
-async_to_sync {ASyncToSync}
-use_dsp48 {UseDSP48}
-iobuf {IOBuf}
-max_fanout {MaxFanOut}
-bufg {BufG}
-register_duplication {RegisterDuplication}
-register_balancing {RegisterBalancing}
-optimize_primitives {OptimizePrimitives}
-use_clock_enable {UseClockEnable}
-use_sync_set {UseSyncSet}
-use_sync_reset {UseSyncReset}
-iob {PackIORegistersIntoIOBs}
-equivalent_register_removal {EquivalentRegisterRemoval}
-slice_utilization_ratio_maxmargin {SliceUtilizationRatioMaxMargin}

Source: https://github.com/VLSI-EDA/PoC/tree/master/xst

Related Solutions

Electronic – List of Xilinx file suffixes (for ISE)

Quick answer: No such list exists, anywhere.

Long answer: I could tell you, but then I'd be wrong. I've been using Xilinx tools for the past 15+ years and every time they come out with a new version (or even a new service pack) things change. Sometimes even just changing various XST/MAP/PAR options will cause new files to be generated. So even if I did give you a list it would likely be out of date or just wrong.

I've created my own makefiles for building my FPGA's (I'm not using ISE's GUI environment), and it's fairly well documented what the input files to the various tools are (XST, MAP, etc). Everything else is not required and thus doesn't need to be checked into the source control system. My makefiles have a "make clean" option that removes all of the extra files. So when Xilinx releases a new version I simply recompile and the "make clean". Any file that remains (and isn't obviously something I need) is considered to be junk, and I add those files to the "make clean" list of things to delete.

Electronic – Using Webpack from the command line, but without a project file

Not that I am aware. Another approach is to use a script instead of a makefile. The script can then create the project file so you do not to manually edit multiple files.

You can use TCL to drive the ISE tools. The ISE tools will generate example code for you. More information on using TCL can be found here, http://devbisme.webfactional.com/blogs/devbisme/2012/04/03/running-weeds

If you want a Python option for building Xilinx ISE projects, see Guenter Dannoritzer's Python scripts, which generate the underling tcl, but the OO interface in Python is better than generating tcl directly, http://www.myhdl.org/doku.php/projects:ise_py. I have made some updates to the scripts here, https://bitbucket.org/cfelton/examples/src/tip/tools

An example, you can quickly and as easily create an ISE project.

# set up pin configuration for the FPGA
fpga = Fpga(path=ppath)
fpga.setPin('clk', 'P124')
fpga.setPin('srst', 'P8')
fpga.setPin('led<0>', 'P92')
fpga.setPin('led<1>', 'P93')
fpga.setPin('led<2>', 'P95')
fpga.setPin('led<3>', 'P96')
fpga.setPin('led<4>', 'P97')
fpga.setPin('led<5>', 'P98')
fpga.setPin('led<6>', 'P99')
fpga.setPin('led<7>', 'P100')
fpga.setDevice('spartan3', 'xc3s400', 'tq144', '-5')

imp = Xilinx(ppath, 'stroby')

imp.setFpga(fpga)
imp.addHdl((vfile))
imp.createTcl() 
imp.run()

Best Answer

Related Solutions

Electronic – List of Xilinx file suffixes (for ISE)

Electronic – Using Webpack from the command line, but without a project file

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