I have encountered an unusual situation in which I require an XOR gate that will function reliably when presented with a square wave input with a frequency between 2 and 3 GHz. I know that desktop CPUs have logic gates that can function at these speeds, but I don't know of any IC that will do this. Should I try to build the gate out of transistors?
Also, at these speeds, do I need to worry about using ground planes, mitered bends, and microstrip?
Best Answer
The fastest logic family long has been and still is ECL. While often overlooked in recent times, developments such as PECL and LVPECL (essentially positive supplty ECL and differential PECL) have kept the family at the forefront of logic switching. The previous limitations of multiple supplies and negative voltages have been eliminated, but with backwards compatability available in many cases.
The MC10EP08 / MC100EP08 devices would meet your requirement http://www.onsemi.com/pub_link/Collateral/MC10EP08-D.PDF
Not quite as good but also almost meeting your spec http://www.onsemi.com/pub_link/Collateral/MC10EL07-D.PDF
Available from Digikey (in stock) http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=MC100EP08DTGOS-ND
In PECL mode these will operate from Vcc = 3.3V to 5V and Vee = 0V.
Maximum frequency is rated as > 3 GHz typical with propogation delays of 250 picosecond (!) typical and 300 picosecond max at 25C with cycle to cycle jitter of < 1 ps.
Digikey list a range of ECL gates.
While 3 GHz operation is probably best left to existing gates such as these ones, it is relatively easy to implement extremely high speed gates yourself using discrete parts with ECL type topology. Looking at the equivalent circuits of older ECL gates gives a good start (modern datasheets typically just give overall functional diagrams with no clues as to how the results are achieved). Gates are essentially very familiar long tailed pair type arrangements. Performance per effort and cost is liable to be vastly better than for most other approaches.
An excellent TI tutorial on "Interfacing Between LVPECL, VML, CML, and LVDS Levels" with discussions on impedance matching, transmission lines, reflections, biasing ... , and includes diagrams of how functionality is achieved.
http://focus.ti.com/lit/an/slla120/slla120.pdf