Electronic – Option to fail Xilinx process if pins are unconstrained

fpgapinoutxilinx

I am using Xilinx WebPack 13.2 and I recall there being a setting to force the Xilinx process to fail if a top level input/output net isn't constrained to a pin. I would like for the process to fail the design flow instead of automatically assigning a pin and finishing the process. Unfortunately I can't seem to find where that option is in the ISE, where is that option in the Xilinx ISE?

Thanks,

Best Answer

I've never found that option - much as I'd love to have it! The closest I've found is the opposite: "fail if there are things constrained which don't exist".

My (Windows CMD.exe) workaround is a post-map script which looks in the .pad file for the string "|UNLOCATED|".

@find "|UNLOCATED|" %DESIGN%.pad || goto padsok

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Electronic – How to assign physical pins of FPGA to Xilinx ISE Verilog modules

Xilinx uses (user constraints file) UCF to bridge the physical pin connections to TOP signals. This file is added to a Xilinx project

the format looks like:

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;
########################################################
#8+2 LED's for indication
########################################################
NET "FPGA_LED<0>" LOC = B21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<1>" LOC = B22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<2>" LOC = C21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<3>" LOC = C22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<4>" LOC = D21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<5>" LOC = D22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<6>" LOC = E22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<7>" LOC = F21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<8>" LOC = F22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<9>" LOC = G22 | IOSTANDARD = "LVCMOS33";
#######################################################
#6 FET/IGBT gate-drive FET-outputs
#######################################################
NET "FPGA_Gate1" LOC = V22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate2" LOC = W22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate3" LOC = W21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate4" LOC = Y22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate5" LOC = Y21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate6" LOC = AA22 | IOSTANDARD = "LVCMOS33";

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;

This is a snapshot from one of my UCF's

Electronic – Xilinx ISE Prevent Trimming For CPU

You can prevent trimming with an option on the Map process properties. In ISE, expand the 'Implement Design' section, and right click 'Map' and select 'Process Properties'

Uncheck the option for 'Trim Unconnected Signals' (-u). Click the help button for more information on all the options displayed here.

From the help:

Trim Unconnected Signals

Specifies whether or not to trim unconnected components and nets from the design before mapping occurs. Leaving this option blank is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, set this property to False (checkbox is blank) to map unconnected components and nets.

By default, this property is set to True (checkbox is checked), and unconnected components and nets are trimmed.

Best Answer

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Electronic – How to assign physical pins of FPGA to Xilinx ISE Verilog modules

Electronic – Xilinx ISE Prevent Trimming For CPU

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