Electronic – Parallel input to serial output

If I understand your question correctly, it is important to understand that the device works in a couple separate stages.

1. The parallel inputs. These have latches that must be signaled to read the inputs and internally hold their state. Once latched, the signal on the input pins can change but the internal signals will be stable. (RCK)
2. The next step is where these internal signals are copied into the shift register. (\$\overline{\small \text{SLOAD}}\$)
3. The last step is shifting out the bits in the shift register (SCK)

If I understand the truth table and timing diagram in the datasheet correctly then the correct order of steps is the following:

1. Initialize the signals as follows RCK = low; \$\overline{\small \text{SLOAD}}\$ = high; \$\overline{\small \text{OE}}\$ = low; SCK = low;
2. Apply parallel signals to the inputs A~H
3. Clock the parallel signals into the latches by driving RCK high. RCK triggers on a rising edge. Drive RCK low, its inactive state.
4. Copy the contents of the input latches into the shift register by driving \$\overline{\small \text{SLOAD}}\$ low. \$\overline{\small \text{SLOAD}}\$ is active low. Drive \$\overline{\small \text{SLOAD}}\$ high again, its inactive state.
5. Read pin Q_H on your MCU
6. Apply a clock pulse on SCK to shift the data out on pin Q_H. SCK triggers on a rising edge. Drive it high, then low.
7. Repeat last 2 steps for as many inputs as you are interested in.

There is quite a lot going on in this diagram.

• The up arrows on the clock are telling you that things are sampled on the positive edge of the clock

• DS is the data going in, you can see that it is sampled on the positive edge of SH_CP. (sample and hold clock, positive edge)

• It the comes out of Q0 on the first positive edge of ST_CP (shift register clock, positive again)

• The pulse then appears at Q1 on the next clock and so on

So the diagram is showing that it is shifting the serial input from one output to the next to the next.

It also shows that bringing MR low resets the internal memory, but outputs Q0-Q7 remain at their state until the next state. The last output, Q7*, seems to change on the negative edge and be reset immediately.

Last of all, if OE(bar) goes high the the outputs all transition to high impedance.

Does that help?