Electronic – How exactly does this shift-register work? – Fairchild 74HC589

picshift-registersignaltiming

I'm using a PISO shift-register, specifically the Fairchild Semiconductor 74HC589.

I got the jist of the workings of a generic shift-register via the very useful animated GIF in Wikipedia link above, although, there is a step that is elluding me:

According to the datasheet, there is a Serial Load pin (13) and a Read Clock pin (12). Supose I just want to load whatever is in the input latches to the shift-register itself and then simply clock the bits out one by one to the serial output pin. What kind of signal/timing sequence am I looking for?

As I figure it out, the serial load pin should be activated to latch the input pins and then the read clock should transfer from the latches to the shift-register, right?

I need to know this because I'm controlling the SR via a PIC32MX and for now I need to know how I can SET or CLEAR the pins I have connected to the SR so I can then read serially in other PIC32 pin.

Any thoughts?

EDIT:

To help everyone understand my question (hopefully) a bit better, each pin on the shift-register is directly connected to a pin in the PIC32. For instance:

    #define READ_CLK                PORTFbits.RF0
    #define READ_CLK_TRIS           TRISFbits.TRISF0

    #define SERIAL_LOAD             PORTEbits.RE4
    #define SERIAL_LOAD_TRIS        TRISEbits.TRISE4

    #define SR_CLK                  PORTEbits.RE3
    #define SR_CLK_TRIS             TRISEbits.TRISE3

    #define SDI_BUS                 PORTEbits.RE2
    #define SDI_BUS_TRIS            TRISEbits.TRISE2

This way, by SETing or CLEARing each signal, I can enable/disable the pins in the shift-register.

In the end, the idea would be to read in the PIC's SDI_BUS pin whatever comes out of the shift-register's QH (pin 9) output.

EDIT2:

I've been searching a bit more about this – I found out it's a technique called bit-banging. I've kinda reduced my particular problem to the chip enable/select phase of what I'm trying to achieve. It isn't very clear to me how the serial load and the read clock pins fit in the picture.

There must be a sequence in which they are brought high (or low) as to enable the clocking out to the QH pin via toggling the serial clock pin. This is fundamentally what I'm trying to understand.

EDIT3:

Following @shuckc's answer I need to clarify the following:

The pin doesn't directly connect the shift-register and the PIC. There are level-shifters between them. Voltage-wise, the signals are correctly adapted.
The fact that the shift-register design being used is 30 years old is out of my control. I'm working on a circuit built with components that have been stored for quite some time and were used to prototype a design concept. I have no other option, ATM.
What I'm trying to understand is the sequence of signals I need to enter at the shift-register so I can output the latched bits serially. This aims to READ into the PIC from the SERIAL OUTPUT of the shift-register.

Right now what I'm trying to do is something in the line of:

enableShiftRegister() // OE pin in SR ->High; SLOAD pin in SR -> High
latchSignal(); // LATCH_PIN = SET; delayNs(2); LATCH_PIN = CLEAR - RCLK in SR
loadSR(); // SLOAD_PIN = CLEAR; delayNs(2); SLOAD_PIN = SET;
for(i=0; i<8; i++){
    clockSR(); // SRCLK_PIN = SET; delayNs(2); SRCLK_PIN = CLEAR; - SRCLK in SR
    sdiBus = SDI_BUS;
}

The delayNs(x) function delays the CPU for x nanoseconds. I also tried to explain which pin in the SR is being controlled by which PIC pin – remember: they are voltage adapted, so that is not a question.

Best Answer

If I understand your question correctly, it is important to understand that the device works in a couple separate stages.

The parallel inputs. These have latches that must be signaled to read the inputs and internally hold their state. Once latched, the signal on the input pins can change but the internal signals will be stable. (RCK)
The next step is where these internal signals are copied into the shift register. (\$\overline{\small \text{SLOAD}}\$)
The last step is shifting out the bits in the shift register (SCK)

If I understand the truth table and timing diagram in the datasheet correctly then the correct order of steps is the following:

Initialize the signals as follows RCK = low; \$\overline{\small \text{SLOAD}}\$ = high; \$\overline{\small \text{OE}}\$ = low; SCK = low;
Apply parallel signals to the inputs A~H
Clock the parallel signals into the latches by driving RCK high. RCK triggers on a rising edge. Drive RCK low, its inactive state.
Copy the contents of the input latches into the shift register by driving \$\overline{\small \text{SLOAD}}\$ low. \$\overline{\small \text{SLOAD}}\$ is active low. Drive \$\overline{\small \text{SLOAD}}\$ high again, its inactive state.
Read pin Q_H on your MCU
Apply a clock pulse on SCK to shift the data out on pin Q_H. SCK triggers on a rising edge. Drive it high, then low.
Repeat last 2 steps for as many inputs as you are interested in.

Related Solutions

Electronic – Strange bug when Interfacing with Shift Register (CPLD) via SPI

Well let's look at your VHDL code. Please keep in mind that I'm not trying to be critical or harsh-- I'm just trying to get you up to speed quickly. Your code is currently this:

process (C, ALOAD) 
begin 
  if (ALOAD='1') then 
    tmp <= "10000001"; 
  elsif (C'event and C='1') then 
    tmp <= tmp(6 downto 0) & '0'; 
    SO <= tmp(7);  
  end if;     
end process;

But should look like this:

process (C, ALOAD)
begin
  if ALOAD='1' then 
    tmp <= "10000001";
  elsif rising_edge(C) then
    tmp <= tmp(tmp'high-1 downto tmp'low) & "0";  -- '0' and "0" are equivalent in this context
  end if;
end process;

SO <= tmp(tmp'high);

The changes I made are minor, for sure, but important.

The first thing is my use of "rising_edge()". This is a new-ish thing to VHDL and isn't covered in some of the VHDL books. This is considered to be better than using 'event. Likewise, there is a falling_edge().

The next thing is my use of 'high and 'low instead of hard-coding the values. This really doesn't matter for this code, but when you start doing bigger things then these will help you a lot. For example, you could just change the definition of tmp to be bigger and the rest of the code will just automatically adjust (except for the initialization to "10000001").

I should also point out that an async reset or load in FPGAs is discouraged, but is fine in CPLDs.

Also note that I moved the assignment of SO to outside the process. This may or may not be what you intended. The way you have it there is an extra flip-flop going from tmp(7) to SO. Normally, with SPI, this isn't want you want because the SPI Clock could go away at the end of the transfer and you'll never get that last bit out. On the other hand, with the way that I did it you'll start getting that first bit out when ALOAD='1', not at the rising edge of C.

Unfortunately, this doesn't really answer your question on why you're getting bad data into the AVR. There just isn't enough information in your question. Here's the kinds of things I would be looking at, or be concerned about:

Your o-scope pic doesn't show the other spi signals, like CS. CS is critical to understanding where the bits are supposed to go. Also, knowing what the SPI mode is will help with this.

On the o-scope pic, the first clock cycle where SO='1' is NOT the first bit of the SPI transfer. You loaded the shift register 10-20 mS before that, and your clock period is about 20 uS. So you had at least 1 clock cycle before SO='1', and probably more. So there is some weird stuff going on here-- we don't have enough info to understand the behavior.

You're using ALOAD to load the shift register, but normally you'd use CS_N (active low). While CS_N='1' you do an async load of the shift register, while CS_N='0' you shift it out. Using ALOAD like you have here is OK, but probably not what you wanted and doesn't work with what appears to be some strange SPI clock stuff (from the previous point).

So, here's what you should do...

Clean up the VHDL a bit. Repost the updated version. Since your scope only has 2 channels, hook up one channel to CS_N and the other channel to CLK. Trigger on the falling edge of CLK. Capture a waveform showing 2 clocks before the falling edge of CLK and 5 clocks after. Without changing the settings on the scope, remove CLK and put the probe on SO. Capture another image. Do this again for the rising edge of CLK. So, 4 waveform images total.

Do that and we can re-evaluate what might be wrong.

Edit: Updated to reflect the updated question.

I see two issues: First, if the AVR is sampling on the rising clk edge, you should clock your shift register off of the falling edge. As supercat mentioned, this will give you +/- 0.5 clock periods of setup & hold going into your AVR.

And Second: As you mentioned, you're getting 10000010 instead of 10000001. I do not believe that your VHDL code is in error on this one, but it is obviously coming out of the CPLD wrong. If I had to guess, I would guess that the problem is with some signal integrity issues with your CLK. It's hard to tell with your scope, but it looks like you have over a volt of overshoot and undershoot on that signal (and with that would come a lot of ringing). That ringing, if bad enough, could cause the CPLD to "double clock"-- meaning run the shift register twice for a single clock edge. And if _really_bad_ it could cause the CPLD to latch up and literally explode (I've seen it happen).

Here's some experiments to try:

Instead of 10000001, use 10101010 or 01010101. This will help you see which bit is getting double clocked, and if it is always the same bit.
Zoom in on the clock edges with the scope. Make sure that your scope probes are at the CPLD, not the AVR, when you do this. Yes, it makes a HUGE difference.

Assuming that it is over/undershoot and ringing on the clock, the solution is to add proper signal termination on the line. I would start with a 50 ohm series resistor at the AVR. Note: this will slow down the clock edges, but since you are clocking the CPLD on the falling edge you have a lot of time available.

How is the clock ran from AVR to CPLD? A long wire between PCB's? That would be my guess.

Electronic – Help me understand this shift register timing diagram

There is quite a lot going on in this diagram.

The up arrows on the clock are telling you that things are sampled on the positive edge of the clock
DS is the data going in, you can see that it is sampled on the positive edge of SH_CP. (sample and hold clock, positive edge)
It the comes out of Q0 on the first positive edge of ST_CP (shift register clock, positive again)
The pulse then appears at Q1 on the next clock and so on

So the diagram is showing that it is shifting the serial input from one output to the next to the next.

It also shows that bringing MR low resets the internal memory, but outputs Q0-Q7 remain at their state until the next state. The last output, Q7*, seems to change on the negative edge and be reset immediately.

Last of all, if OE(bar) goes high the the outputs all transition to high impedance.

Does that help?

Best Answer

Related Solutions

Electronic – Strange bug when Interfacing with Shift Register (CPLD) via SPI

Electronic – Help me understand this shift register timing diagram

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