I think you're on the right path, a couple of notes,
1) With a signal trace between two planes, the return current will split between the two planes, even if one of the planes is split. The return current cannot "see the future" and decide ahead of time which plane to return on. It will return above and below the trace until it sees the split at which point is says "oh crap!" and pays you back by possibly causing you to fail FCC testing. So you want to avoid running traces over plane splits even if another adjacent plane is not split. You can deal with splits with capacitors and such but this type of solution is less than ideal. I'd focus on always avoiding running a trace over a plane split on an adjacent plane.
2) Wide return paths on DC signals don't really matter.
3) You asked about two signal layers sharing the same plane. Usually, this is not a big deal if done properly. What many people do is use one of the layers as a "horizontal" signal layer and the other as a "vertical" signal layer so the return currents are orthogonal to each other. It is very common to route two signal layers for each plane, and use this horizontal/vertical technique. The most important thing to remember is to not change reference planes. Your setup could be a little tricky because going from the bottom layer to the 4th layer adds another return plane. More typical 6 layer boards are
1)ASignalHor 2)GND 3)ASignalVer 4)BSignalHor 5)POWER 6)BSignalVer
If you need smaller additional planes, like under the micro, these would usually be placed as an island on one of the signal layers. If you need to use more power planes, you might want to think about going to 10+ layers.
4) Plane spacing is important, and can have huge impact on performance, so you should specify this to the board house. If you take the example 6 layer stackup I mentioned above, spacing of .005 .005 .040 .005 .005 (instead of standard stackup with equal distance between layers) can make an order of magnitude improvement. It keeps the signal layers close to their reference plane (smaller loops).
First of all, before answering your questions, let me make some suggestions about the layout. I have seen your previous post and this has been a good attempt, but:
1.- The "Switching Loog" is too large. (Switching loop is Vin, Trafo, Q1 and R8, you call it,"high current loop", maybe it is no quite precise) And moreover, this loop include the control area. This is really EMI problem!! I suggest something like this.
(Think in current loops always!)
Make smaller the switching loop
- Place R8 near from C1. Really near.
- Rotate Q1 90ยบ clockwise
- Place R6 and C6 as close as possible (acap) from Trafo pins.
After that,
- Think about the "Gate net", "Sense net" and "pin 15 from controller net", It must be route separatly! The "gate net" is a radiant net and the others ones are sensitive nets. Route them.
- Route Vin and Enable controller nets.
- Complete the route of primary
(The controller has not a Decoupling Capacitor ? Are you sure of this?)
2.- A connector for trasformer sounds a problems maker. Could you solder your Custom Transforme in the PCB? It would be better. If you cann't, I you sugggest a 2 row 2 columns conectors. In this way you can gain more space between primary and secondary, and more space between trafo pins.
OK and now. Your questions.
1.- Yes, try to keep separate switching ground from control ground, but connect to the same ground, in your case Bottom layer. For this, try to keep the "switching loop" components together according the placement I suggest.
Connecting R8 to Vin through one track and then one via to GND is not a good idea in your current layout.
2.- Ummm... I would try another layout before consider this question.
3.- I cann't undestand this question. What do you mean?
4.- As a rule, It better If you fill the empty area with hatched copper. It improve the etching process in PCB manufactureing.
5.- As a starting point, fill as much as you can. Do you need consider any electrical isolation between primary and secondary.
Good luck!
Best Answer
You could do that, but it's not generally done because the higher the frequency, the less of an issue EMC is. Frequencies that cause EMC issues are generally high enough that the return path follows the red line. Unless you have some extreme EMC requirements at frequencies below about 10MHz, or sensitive magnetic instruments nearby, it's not usually necessary.