The only way I though to counter act this is to AND the flip flop's clock input with a clock that is faster than the main clock... that way data will be guaranteed to be clocked in at the end of that cycle.
This sounds to me like an architecture choice that will eventually limit the performance (maximum clock speed) you can achieve with your design. If your registers are able to function at the faster clock speed, you'll eventually want to try to get the whole system running as close to that clock speed as you can, but then you won't be able to have a "slow" clock and a "fast" clock to do this with.
In order to do this, I'm fetching data from memory, placing it on the data bus, then clocking it into a register all in a single operation. I'm worried that the rising edge of the main clock will happen at the register before the data is fetched from memory.... a sort of propagation delay / race condition.
First solution
One way that leaps to mind to solve this is to clock data out of the memory on the rising edge of the clock, and clock it in to the register on the falling edge. Since your register doesn't have a configuration bit for which edge it responds to (like it would if you were designing in an FPGA), you would have to generate the appropriate signal by using an inverter (NOT gate) between the "main" clock signal and the register.
More generally, it's possible to distribute several phases of your clock (e.g., 0, 90, 180, and 270 degrees) instead of just clock and inverted clock. And use these different phases to execute different actions at different times. Of course you have to do a fairly careful analysis of each interface where data is transferred from one phase to another to be sure setup and hold times are met.
To the best of my understanding (possibly out-of-date) multiphase clock designs were fairly common in the discrete logic design era, and were also common (and may still be common) in ASICs and custom chip designs. But they are fairly uncommon in FPGA design due to the complexity of the timing analysis.
Second solution
Another option is to create a controller state machine that enables and disables different elements on different clock cycles as needed. For example, you'd enable the memory output on cycle 1 and enable the register to latch in the data on cycle 2. Since your register apparently doesn't have a clock enable input, you might need to do this by ANDing a state machine output with the clock input to the register.
This type of design was fairly common in the era of discrete logic CPUs, and its what was taught in undergraduate digital logic courses in the early 90's. An elaborate version of this scheme is called a microcoded architecture.
Of course this architecture means that you need more than one clock cycle to complete each instruction. But it would be multiple cycles of your fast clock, not your original "slow" clock that would be used, and you are already using more than one cycle of the fast clock per instruction in your design.
"What does it mean when a flip flop performs a function like SET, CLEAR, HOLD, or TOGGLE?"
first I'll like you to explain about latches.There is not much difference between latches and flipflop.Latches don't have clock input but flipflop have clock inputs.Here is a simple Set-Reset latch
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Explanation for SET:From the name,it suggests that,when you apply Logic HIGH to 'S'(Set),this sets the output Q to logic HIGH.The not(Q) will be it complement(logic LOW)
.Explanation for RESET:If you apply logic HIGH to 'R'(Reset),it makes the output Q to logic LOW,then not(Q) will be HIGH.(note that 'S' should be in logic LOW at that time).
Explanation for HOLD:If you apply Logic LOW to both input(S and R),The output doesn't change.I mean,it HOLDS the past output.
Explanation for TOGGLE:If you apply both pins with logic HIGH,it leads to indeterminate state for SR latch and it's the limitation of SR latch,so if you consider J-K flipflop,when you apply both J and K with Logic HIGH,it changes the output(ie. output HIGH goes to LOW and vice versa).This is called as TOGGLING.
"I start with a clock signal that goes into each flip flop. From there, I really have no clue how to trace what's going on."
Please note that,clock signal is to activate the latch circuit.A Latch with Clock pulse is called as Flipflop.Applying clock signal to activate a latch is called as Triggering.There are two types of triggering.One is edge triggering and the other is level triggering.
.In level triggering,The flipflop is ready to get the input throughout the Level of the clock continuous.In edge triggering,The flipflop will be ready to get input only when the edge of the clock is detected.Always edge triggering is preferred.
Best Answer
There isn’t a hold time problem if you add an inverter - in fact this helps hold time, but subtracts from setup time.
No flip-flop is guaranteed to power up in a known state. They all require a set or reset to initialize them. You’ll need to add this, or design your logic so that it doesn't care.
As you said, the ‘79 flip flop could be initialized to a known state by forcing the input and clocking it. This requires an additional gate to the D input, and coordinating that state-forcing with toggling the clock. Probably more complicated than you want.
The ‘175 flip-flop has an asynchronous reset, which works regardless of the clock. You could indeed do some kind of RC circuit to make a reset at power on for a cheap-and-cheerful solution.
Finally, static flip-flops like these have no maximum clock period / minimum frequency. Dynamic flip-flops exist, but not as small ICs like the ones you’re working with here.