I'm trying to connect clock divider generated by CORE Generator to I2S receiver and I2S transmitter on Spartan 6. The PLL_BASE is connected via ODDR2 module, as adviced. Both receiver and transmitter work when clocks are divided without block from CORE Generator.
Code
clk_wiz_v3_6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
mclk : out std_logic;
sclk : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end clk_wiz_v3_6;
architecture xilinx of clk_wiz_v3_6 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
signal clk0obuf : std_logic;
signal clk0bufg : std_logic;
signal notclk0bufg : std_logic;
signal clk1bufg : std_logic;
signal notclk1bufg : std_logic;
signal clk1obuf : std_logic;
begin
notclk0bufg <= clk0bufg;
notclk1bufg <= clk1bufg;
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 4,
CLKFBOUT_MULT => 29,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 59,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 118,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 10.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => locked_unused,
RST => RESET,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => clk0obuf, -- 1-bit output data
C0 => clk0bufg, -- 1-bit clock input
C1 => NOTclk0bufg, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1',
D1 => '0',
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
ODDR2_inst2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => clk1obuf, -- 1-bit output data
C0 => clk1bufg, -- 1-bit clock input
C1 => NOTclk1bufg, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '1',
D1 => '0',
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => clk0bufg, --mclk
I => clkout0);
clkout2_buf : BUFG
port map
(O => clk1bufg, --sclk
I => clkout1);
clkout3_buf : OBUF
port map
(O => mclk, --mclk
I => clk0obuf);
clkout4_buf : OBUF
port map
(O => sclk, --sclk
I => clk1obuf);
end xilinx;
i2sClocks.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity i2sClocks is
port
(
clk : in std_logic;
lrclk : out std_logic
);
end i2sClocks;
architecture rtl of i2sClocks is
signal i2sClocksDivider_i :std_logic_vector(6 downto 0) := (others => '0');
begin
lrclk <= i2sClocksDivider_i(6);
process(clk)
begin
if rising_edge(clk) then
i2sClocksDivider_i <= std_logic_vector(unsigned(i2sClocksDivider_i) + 1);
end if;
end process;
end rtl;
receiver.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity i2sReceiver is
port(
serialClock : in std_logic;
wordSelect : in std_logic;
serialData : in std_logic;
lastSample : out std_logic_vector(23 downto 0) := (others => '0')
);
end i2sReceiver;
architecture rtl of i2sReceiver is
signal currentSample_i : std_logic_vector(23 downto 0) := (others => '0');
signal currentSampleIndex_i : std_logic_vector(5 downto 0) := (others => '0');
signal lastWordSelect_i : std_logic;
begin
process(serialClock)
begin
if rising_edge(serialClock) then
currentSampleIndex_i <= std_logic_vector(unsigned(currentSampleIndex_i) + 1);
if currentSampleIndex_i(4 downto 0) < "11000" then
currentSample_i(to_integer(unsigned(currentSampleIndex_i(4 downto 0)))) <= serialData;
end if;
if (lastWordSelect_i = (not lastWordSelect_i)) then
lastWordSelect_i <= wordSelect;
if lastWordSelect_i = '1' then
currentSampleIndex_i <= (others => '0');
end if;
end if;
end if;
if falling_edge(serialClock) then
if ((currentSampleIndex_i = "011100") or (currentSampleIndex_i = "111100")) then
lastSample <= currentSample_i;
end if;
end if;
end process;
end rtl;
transmitter.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity i2sTransmitter is
port (
serialClock : in std_logic;
wordSelect : in std_logic;
serialData : out std_logic;
lastSample : in std_logic_vector(23 downto 0)
);
end i2sTransmitter;
architecture rtl of i2sTransmitter is
signal currentSample_i : std_logic_vector(23 downto 0) := (others => '0');
signal currentSampleIndex_i : std_logic_vector(5 downto 0) := (others => '0');
signal lastWordSelect_i : std_logic;
begin
process(serialClock)
begin
if rising_edge(serialClock) then
currentSampleIndex_i <= std_logic_vector(unsigned(currentSampleIndex_i) + 1);
if (lastWordSelect_i = (not lastWordSelect_i)) then
lastWordSelect_i <= wordSelect;
if lastWordSelect_i = '1' then
currentSampleIndex_i <= "000001";
end if;
end if;
end if;
if falling_edge(serialClock) then
if ((currentSampleIndex_i = "011100") or (currentSampleIndex_i = "111100")) then
currentSample_i(23 downto 0) <= lastSample;
end if;
if currentSampleIndex_i(4 downto 0) < "11000" then
serialData <= currentSample_i(to_integer(unsigned(currentSampleIndex_i(4 downto 0))));
end if;
end if;
end process;
end rtl;
top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity box is
port(
clk : in std_logic;
reset : in std_logic;
adcSerial : in std_logic;
mclkAdc : out std_logic;
sclkAdc : out std_logic;
lrclkAdc : out std_logic;
dacSerial : out std_logic;
mclkDac : out std_logic;
sclkDac : out std_logic;
lrclkDac : out std_logic
);
end box;
architecture Behavioral of box is
component clk_wiz_v3_6 is
port
(
clk_in1 : in std_logic;
mclk : out std_logic;
sclk : out std_logic;
reset : in std_logic
);
end component;
component i2sClocks is
port
(
clk : in std_logic;
lrclk : out std_logic
);
end component;
component i2sReceiver is
port(
serialClock : in std_logic;
wordSelect : in std_logic;
serialData : in std_logic;
lastSample : out std_logic_vector(23 downto 0)
);
end component;
component i2sTransmitter is
port(
serialClock : in std_logic;
wordSelect : in std_logic;
serialData : out std_logic;
lastSample : in std_logic_vector(23 downto 0)
);
end component;
signal mclk_i : std_logic;
signal sclk_i : std_logic;
signal lrclk_i : std_logic;
signal dacSerial_i: std_logic;
signal sample_i : std_logic_vector(23 downto 0);
begin
mclkAdc <= mclk_i;
sclkAdc <= sclk_i;
lrclkAdc <= lrclk_i;
mclkDac <= mclk_i;
sclkDac <= sclk_i;
lrclkDac <= lrclk_i;
dacSerial <= dacSerial_i;
clocks: clk_wiz_v3_6
port map
(
clk_in1 => clk,
mclk => mclk_i,
sclk => sclk_i,
reset => reset
);
clocks2: i2sClocks
port map
(
clk => sclk_i,
lrclk => lrclk_i
);
adc: i2sReceiver
port map
(
serialClock => sclk_i,
wordSelect => lrclk_i,
serialData => adcSerial,
lastSample => sample_i
);
dac: i2sTransmitter
port map
(
serialClock => sclk_i,
wordSelect => lrclk_i,
serialData => dacSerial_i,
lastSample => sample_i
);
end Behavioral;
constrains-clean.ucf
CONFIG VCCAUX = "3.3" ;
NET "clk" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz;
NET "reset" LOC = C17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "dacSerial" LOC = T11;
NET "sclkDac" LOC = T10;
NET "lrclkDac" LOC = V13;
NET "mclkDac" LOC = V11;
NET "adcSerial" LOC = H17;
NET "sclkAdc" LOC = H18;
NET "lrclkAdc" LOC = J18;
NET "mclkAdc" LOC = K16;
Build results
-
When clock divider from CORE Generator is connected to outputs (receiver), sythesis and implemetation are successful.
-
When clock divider from CORE Generator is connected to receiver's and transmitter's outputs, I get errors:
ERROR:ConstraintSystem:59 - Constraint <NET "sclkAdc" LOC = H18;> [constrains-clean.ucf(13)]: NET "sclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "sclkAdc" LOC = H18;> [constrains-clean.ucf(13)]' could not be found and so the Locate constraint will be removed. ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc" LOC = K16;> [constrains-clean.ucf(15)]: NET "mclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "mclkAdc" LOC = K16;> [constrains-clean.ucf(15)]' could not be found and so the Locate constraint will be removed. -
When clock divider from CORE Generator is connected to receiver's and transmitter's outputs and to additional divider used to generate LRCLK, I get errors:
ERROR:ConstraintSystem:59 - Constraint <NET "sclkAdc" LOC = H18;> [constrains-clean.ucf(13)]: NET "sclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "sclkAdc" LOC = H18;> [constrains-clean.ucf(13)]' could not be found and so the Locate constraint will be removed. ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc" LOC = K16;> [constrains-clean.ucf(15)]: NET "mclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "mclkAdc" LOC = K16;> [constrains-clean.ucf(15)]' could not be found and so the Locate constraint will be removed. Done... Checking expanded design ... ERROR:NgdBuild:809 - output pad net 'sclkDac' has an illegal load: pin C on block clocks2/i2sClocksDivider_i_0 with type FD, pin C on block clocks2/i2sClocksDivider_i_1 with type FD, pin C on block clocks2/i2sClocksDivider_i_2 with type FD, pin C on block clocks2/i2sClocksDivider_i_3 with type FD, pin C on block clocks2/i2sClocksDivider_i_4 with type FD, pin C on block clocks2/i2sClocksDivider_i_5 with type FD, pin C on block clocks2/i2sClocksDivider_i_6 with type FD -
When clock divider from CORE Generator is connected to receiver's and transmitter's outputs,to additional divider used to generate LRCLK and to I2S modules in project, I get errors:
WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "sclkAdc" LOC = H18;> [constrains-clean.ucf(13)]' could not be found and so the Locate constraint will be removed. ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc" LOC = K16;> [constrains-clean.ucf(15)]: NET "mclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "mclkAdc" LOC = K16;> [constrains-clean.ucf(15)]' could not be found and so the Locate constraint will be removed. WARNING:NgdBuild:1012 - The constraint <NET "sclkAdc" LOC = H18;> [constrains-clean.ucf(13)] is overridden on the design object sclkDac by the constraint <NET "sclkDac" LOC = T10;> [constrains-clean.ucf(8)].
To be honest, I spend a few days trying to solve it but with no luck. What should I do to succesfully connect clock divider from CORE Generator and build project without errors?
EDIT:
Thanks to @Paebbels, warnings about wordSelect and currentSampleIndex_i_5 are no longer occuring. Following his advices, I changed design as follows:
- In constraints.ucf pin reset is assigned only to location and I/O standard and so does every other pin besides clk (i.e.
LOC = T10 | IOSTANDARD = LVCMOS33;). currentSampleIndexin both transmitter and receiver is now written as unsigned.currentSampleIndexand every assignment or condition with it is trimmed to 5 bits- The condition in transmitter and receiver is now
if (wordSelect = (not lastWordSelect_i))
Fatal errors
Errors and warnings occuring durign compilation are now as follow:
-
When clock divider from CORE Generator is connected to receiver's and transmitter's outputs and to additional divider used to generate LRCLK
Clock Information: ------------------ -----------------------------------+-----------------------------------+------ -+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+-----------------------------------+-------+ clocks/clk1obuf | NONE(clocks2/i2sClocksDivider_i_0)| 7 | clocks/pll_base_inst/CLKOUT1 | BUFG | 1 | clocks/pll_base_inst/CLKOUT0 | BUFG | 1 | -----------------------------------+-----------------------------------+------ -+ INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. (...) ERROR:ConstraintSystem:59 - Constraint <NET "sclkAdc" LOC = H18 |> [constrains-clean.ucf(13)]: NET "sclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "sclkAdc" LOC = H18 |> [constrains-clean.ucf(13)]' could not be found and so the Locate constraint will be removed. ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33;> [constrains-clean.ucf(13)]: NET "sclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc" LOC = K16 |> [constrains-clean.ucf(15)]: NET "mclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "mclkAdc" LOC = K16 |> [constrains-clean.ucf(15)]' could not be found and so the Locate constraint will be removed. ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33;> [constrains-clean.ucf(15)]: NET "mclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. Done... Checking expanded design ... ERROR:NgdBuild:809 - output pad net 'sclkDac' has an illegal load: pin C on block clocks2/i2sClocksDivider_i_0 with type FD, pin C on block clocks2/i2sClocksDivider_i_1 with type FD, pin C on block clocks2/i2sClocksDivider_i_2 with type FD, pin C on block clocks2/i2sClocksDivider_i_3 with type FD, pin C on block clocks2/i2sClocksDivider_i_4 with type FD, pin C on block clocks2/i2sClocksDivider_i_5 with type FD, pin C on block clocks2/i2sClocksDivider_i_6 with type FD -
When clock divider from CORE Generator is connected to receiver's and transmitter's outputs,to additional divider used to generate LRCLK and to I2S modules in project
INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_0> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_0> INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_1> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_1> INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_2> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_2> INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_3> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_3> INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_4> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_4> INFO:Xst:2261 - The FF/Latch <adc/currentSampleIndex_us_5> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/currentSampleIndex_us_5> INFO:Xst:2261 - The FF/Latch <adc/lastWordSelect_i> in Unit <box> is equivalent to the following FF/Latch, which will be removed : <dac/lastWordSelect_i> (...) WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "sclkAdc" LOC = H18 |> [constrains-clean.ucf(13)]' could not be found and so the Locate constraint will be removed. ERROR:ConstraintSystem:59 - Constraint <NET "mclkAdc" LOC = K16 |> [constrains-clean.ucf(15)]: NET "mclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:ConstraintSystem - A target design object for the Locate constraint '<NET "mclkAdc" LOC = K16 |> [constrains-clean.ucf(15)]' could not be found and so the Locate constraint will be removed. ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33;> [constrains-clean.ucf(15)]: NET "mclkAdc" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. WARNING:NgdBuild:1012 - The constraint <NET "sclkAdc" LOC = H18 |> [constrains-clean.ucf(13)] is overridden on the design object sclkDac by the constraint <NET "sclkDac" LOC = T10 |> [constrains-clean.ucf(8)]. WARNING:NgdBuild:1012 - The constraint <IOSTANDARD = LVCMOS33;> [constrains-clean.ucf(13)] is overridden on the design object sclkDac by the constraint <IOSTANDARD = LVCMOS33;> [constrains-clean.ucf(8)].
Best Answer
It looks like the pins in your top module disagree with the constraints file.