Electronic – Push pull CMOS output stage overcoming the distortion problem


I implemented the simple push pull source follower and I understand that it has this distortion problem. That is between -|VTP| ≤ Vin ≤ VTN there is no output because the output terminal floats since both the transistor are not conducting. I hope my understanding is correct.

Simple push pull stage

In order to avoid this distortion problem there is this push pull with quiescent current output stage shown below.

push pull with quiscent current

These are my following questions,

1) How does this new model correct the distortion problem?

2) Should all M3,M4,M5 and M6 be in saturation?

3) Is there any hint on how I could dimension these transisitors?

Also Vss in my case is 0. Any feedback would be much appreciated 🙂

Best Answer

1.) The transistors M4 and M5 act like a floating voltage source. M3 is a current source and therefore the voltage across M4 and M5 is constant.

M6 and M3 form a common-source stage that allows to move the floating voltage source up and down. This eliminates the region where neither M1 nor M2 is conducting, therefore distortion is reduced.

2.) All these transistors should be in saturation. M4, M5 will always be in saturation since they are diode-connected.

3.) The dimensioning is usually done for the quiescent condition where the output signal is zero. For this case M4/M1 and M5/M2 act like current mirrors.

The ratio determines the quiescent current.