A flip-flop can only change state when there is a zero-to-one transition in the incoming clock. If J=1 and K=1, Q output will toggle at half the frequency of the CLK.
It may help you (or confuse you) to know that internally a flip-flop can be formed by cascading two level-sensitive latches, the first of which is low-level latching and the second one is high-level latching. When the same clock is fed to both latch enables, the first latch will settle its state when the clock signal (its latch enable) is low. The second latch will settle its state when the clock signal (its latch enable) is high. Note that the input of the second latch is the output of the first latch. The end result is an edge-sensitive device.
At a glance to get your circuit, the wiring seems wrong, in halfclk you had:
dff dff1(clk, reset, d, q, qb);
dff dff2(w1, reset, d1, w2, qb1);
Shouldn't it be (renaming a little bit for clarity):
input clk, reset;
output q1, q2;
wire qb1, qb2;
dff dff1(clk, reset, qb1, q1, qb1);
dff dff2(q1, reset, qb2, q2, qb2);
However a warning: If you use the q output to the clock, a real circuit will add up a significant delay. That's bad for a number of reasons. In some circumstances it's ok though, if you don't care about the phase relationship. If you do care, then look into designing a synchronous counter. Also, for a real circuit, buffer the output from the counter, otherwise if you just pass out q or qb it might see a big load and your counter will (at best) slow down even more.
Best Answer
Assuming your input clock is reasonably symmetric, you can use both edges of it, like this:
simulate this circuit – Schematic created using CircuitLab
As long as the input duty cycle is close to 50%, the output will have two pulses for every three input pulses. The top part is a simple divide-by-three with a 1/3 duty cycle, and the extra FF on the bottom creates a second set of output pulses that happen midway between the first set. They get combined together by the final NOR (or OR) gate.