Behavioral code is higher-level and usually can't be synthesized. Constructs like loops, delays, and "initial" statements are behavioral.
RTL code is lower-level and is intended to be synthesized. It defines a circuit as a combination of interconnected registers and the operations performed on signals between those registers.
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re: (fair question but now deleted) in comments : HDL Designer is a professional tool for logic design from Mentor Graphics. It has been around for a while, originally under the Renoir name, it's only been HDL Designer for about six or seven years.
It intends to add higher levels of abstraction over VHDL and Verilog designs. From what I have seen of Verilog, it might be useful there, but if you're using VHDL you can write at a higher level of abstraction without it, and using HDL Designer badly can keep your VHDL code stuck in the dark ages...
However, that said :
a Library, like a VHDL library, is for things (types, components, packages, utilities) that you will re-use in different places, either within a single project or common to multiple projects.
A Project is what you would use to structure a single design, e.g. for a single FPGA, the testbench for it, and possibly the board it is on.
One reasonable use of HDL Designer is to create wrappers for substantial VHDL components (CPU, memory, bus interface, FFT processor etc) and to create structural VHDL designs using them, in the form of HDL Designer block diagrams. That way you effectively have compilable documentation...
Best Answer
HDL is the catch all name for all hardware definition languages (Verilog, VHDL, etc.) in the same way Object Oriented can refer to C++, Java, etc.
RTL on the other hand is a way of describing a circuit.
You write your RTL level code in an HDL language which then gets translated (by synthesis tools) to gate level description in the same HDL language or whatever your target device/process will take.
Let me give you an example. Here is a line of Verilog (HDL) describing a mux in RTL:
Your synthesis tool can take that and convert it to a set of logic gates, or just a mux macro that is supported by your end device. For example it might instantiate a mux macro
In both cases you can feed the same inputs to the block (RTL, or gate-level) and your output should be the same. In fact there are tools that check the output of your synthesis against your RTL code to make sure the tool didn't accidental optimize or change something during synthesis that caused a mismatch. This is called Formal Verification.
For a variety of reasons, interoperability, ease of change, understandability you write your description of the digital circuit as RTL, instead of gate-level.