Which should I use? I'd like to use it to model circuits for homework and to possibly reuse parts circuits in other designs.
HDL Designer: What’s the difference between a project and a library
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HDL is the catch all name for all hardware definition languages (Verilog, VHDL, etc.) in the same way Object Oriented can refer to C++, Java, etc.
RTL on the other hand is a way of describing a circuit.
You write your RTL level code in an HDL language which then gets translated (by synthesis tools) to gate level description in the same HDL language or whatever your target device/process will take.
Let me give you an example. Here is a line of Verilog (HDL) describing a mux in RTL:
assign mux_out = (sel) ? din_1 : din_0;
Your synthesis tool can take that and convert it to a set of logic gates, or just a mux macro that is supported by your end device. For example it might instantiate a mux macro
mux u3 (mux_out, din_1, din_0);
In both cases you can feed the same inputs to the block (RTL, or gate-level) and your output should be the same. In fact there are tools that check the output of your synthesis against your RTL code to make sure the tool didn't accidental optimize or change something during synthesis that caused a mismatch. This is called Formal Verification.
For a variety of reasons, interoperability, ease of change, understandability you write your description of the digital circuit as RTL, instead of gate-level.
i'm not familiar with all on your list. I see TAPR as analogous to GPL, and good applicability to HDL. others may be tricky. I've wished for a TAPR sort of thing designed for hardware/hdl code that is more like LGPL, but i haven't seen one like that.
GPL, LGPL, BSD etc. are written for copyrighted stuff, and that sortof leaves open a loophole for hardware designs. you don't "publish" an asic, so there can be a breakdown in legalese fitment there. FPGAs may be slightly better fit, as for fpga you do something comparable to compiling spurce code, and distributing the bitfile is a little closer to publishing something you can copyright than doing PnR for a hardwired asic, and you can make your fpga design updatable by downloading and installing new bitfile, which is like getting and using a lot of software today, but it's still muddy waters for copyright based licensing.
i'm also not sure of cross-compatibility between the copyright licenses and the hardware-specific licenses.
IMHO, of the ones i've read, TAPR is best, but like gpl makes your entire project open-source under TAPR. I's prefer to see cores under an lgpl analog. contribute improvements to the ip core, but protect other parts of the design.
as i understand, the copyright license weirdities are enforcemen t related. so mostly a problem if you sue a user that didn't follow the intent of the license, they may get off on technicalities.
Best Answer
re: (fair question but now deleted) in comments : HDL Designer is a professional tool for logic design from Mentor Graphics. It has been around for a while, originally under the Renoir name, it's only been HDL Designer for about six or seven years.
It intends to add higher levels of abstraction over VHDL and Verilog designs. From what I have seen of Verilog, it might be useful there, but if you're using VHDL you can write at a higher level of abstraction without it, and using HDL Designer badly can keep your VHDL code stuck in the dark ages...
However, that said :
a Library, like a VHDL library, is for things (types, components, packages, utilities) that you will re-use in different places, either within a single project or common to multiple projects.
A Project is what you would use to structure a single design, e.g. for a single FPGA, the testbench for it, and possibly the board it is on.
One reasonable use of HDL Designer is to create wrappers for substantial VHDL components (CPU, memory, bus interface, FFT processor etc) and to create structural VHDL designs using them, in the form of HDL Designer block diagrams. That way you effectively have compilable documentation...