Electronic – Sequential Circuit Diagram: D Flip-Flop

The easiest flip-flop to understand is the SR (Set-Reset) flip-flop:

Normally both inputs are high. When you pull the \$/S\$ input low, output \$Q\$ will go high regardless of the other input. Since the other NAND gate sees now a high level on both its inputs the \$/Q\$ output will be low. Now, even when \$/S\$ goes high again, the other input will be low, so the output \$Q\$ retains its state. That's the most easy way to make logic "remember" something.

Starting from the SR flip-flop you can make more complicated registered logic, where the D flip-flop is the most used.

This circuit is sometimes presented as an edge-triggered D -flipflop, but it's really level triggered, where \$CLK\$ is used to gate the \$D\$ input. If \$CLK\$ is low both inputs of the SR flip-flop are high, and it retains its output state. When \$CLK\$ goes high the \$D\$ input decides whether \$/S\$ or \$/R\$ goes low, and the output will set accordingly, thus remembering the state of \$D\$ when \$CLK\$ went high. The difference with a real edge-triggered D -flip-flop is that the output will change with the input as long as \$CLK\$ is high. To make it an edge-triggered flip-flop you'll have to include some feedback that makes the \$CLK\$ go low again immediately after going high. The D-type latch, as it's called, will remember the input state at the time the \$CLK\$ input goes low; i.e. the output will stop changing after the \$CLK\$ goes low again.

This is an edge-triggered D flip-flop:

I think the things that is really missing from your design are signals, signals exist inside the architecture and can be assigned in much the same way as a port but without an interface to the outside world, a signal can be written to and read from and can be any type you like and an output can be assigned a signal of the same type so for your design consider using an internal register and then assigning it to your output.

Here's an example of what I mean:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;

entity lfsr is

    port (

        -- Clocks
        clkin                                   :in  STD_LOGIC; 

        -- Initialisation data
        first_key                               :in  STD_LOGIC_VECTOR(3 downto 0);

        -- Control Signals
        key_set                                 :in  STD_LOGIC;
        push                                    :in  STD_LOGIC;

        -- Outputs
        data_out                                :out STD_LOGIC_VECTOR(3 downto 0);              
        );

end lfsr;   

architecture RTL1 of lfsr is    

    signal key                      :STD_LOGIC_VECTOR(3 downto 0);

begin                                                                                                               

    -- Generate a key every time the push signal is asserted
    process(clkin)
    begin

        if rising_edge(clkin) then

            if key_set = '1' then -- Initialises the key

                key <=  first_key; 

            elsif push = '1' then -- Generate a new key

                key(2 downto 0) <=  key(3 downto 1);
                key(3)          <=  key(1) XOR key(0);

            end if;

        end if;

    end process;

    -- Send internal key to output port
    data_out    <=  key;

end RTL1;

so the signal that I have created is key, it is internal to the architecture and what it actually represents is a block of memory 4 bits wide. This code actually does what you want, it is a LFSR that will generate pseudo random data but I have made it 4 bits wide instead of 8 because I didn't want to just give you the answer and if you can understand what this code does, you will be able to understand how to expand it to 8-bits and it will be a great start to understanding VHDL.

If you have any questions about my code then please ask,

Gipsy