Electronic – Set STD_LOGIC_VECTOR with constant integer

vhdl

Is it possible to set a STD_LOGIC_VECTOR(6 DOWNTO 0) with a constant like so:

signal s1: std_logic_vector(6 downto 0);
s1 <= 12;

Or do I have to define it as a set of bits?

Best Answer

You can do it, but not directly. Something like this should work:

s1 <= std_logic_vector(to_unsigned(12,7));

s1 <= std_logic_vector(to_unsigned(12,s1'length));

Of course at the begining of your file you should declare:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Related Solutions

Electronic – VHDL logical operation on integer

A better way than using std_logic_vector and the non-standard std_logic_arith and std_logic_signed libraries is to use IEEE.numeric_std.all; and make the counter unsigned (or signed in other contexts where you need negative values).

signal hcount  : unsigned(7 downto 0);

And you can perform conversions to and from integer, and bitwise operations:

hcount <= to_unsigned(123,hcount'length);

signal somereg : std_logic_vector(7 downto 0);
...
somereg(to_integer(hcount(2 downto 0)) <= <a bit value>;

However in the given example, the bitwise operations turn out to be unnecessary: instead of masking bits to extract a 3-bit register address, you could use division and mod operations. Synthesis tools (mostly) aren't stupid : divide and mod by powers of 2 are optimised into the obvious field extractions and don't even generate "and" gates.

signal hcount    : natural range 0 to 235;
signal reg_addr  : natural range 0 to 7;

signal somereg : std_logic_vector(7 downto 0);
...
reg_addr <= hcount mod 8;
somereg(reg_addr) <= <a bit value>;

One benefit of this (apart from fewer ugly type conversions) is that you still profit from the integer subtype you declared for hcount : incrementing it to 236 will raise an overflow error in simulation, allowing you to catch and correct logic errors early.

Loading hex and binary data at the same time from text file into std_logic_vector

The basic process is to

Open the file for reading using file_open().
Loop over each line until end-of-file is encountered:
1. Read the line to a variable of type line using readline().
2. Read the line as a string using read().
3. Separate the string into the two parts you're interst using indeces.
4. Convert the strings character-by-character to std_logic_vectors using a conversion function (I can't find a built in one - I might be missing the obvious - but it's just a simple case statement with cases for all of the characters you're interesed in and a flag or assert for any unexpected ones).

There's plenty of examples for the file IO part:

Best Answer

Related Solutions

Electronic – VHDL logical operation on integer

Loading hex and binary data at the same time from text file into std_logic_vector

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