ltspicemosfetvoltage
I am new to all this, so please forgive me, as I feel the answer to this must be so simple.
I tried to build a basic CMOS switch. It has a supply of 5 V. There are periodic pulses of 5 V supplied to the input.
I expected the output to alternate between 0 V and 5 V. After running the simulation, I was surprised to find out that it alternates between 0 V and 620 mV.
Either I am not understanding things correctly, or there is something wrong here. Why am I not seeing 5 V on the output?
Your boost is operating in discontinuous conduction mode or DCM (inductor current goes to zero each switching cycle). The duty cycle becomes a function of load as well as the duty cycle. If you increase the load, the inductor value, or switching frequency, you'll reach a point where you'll see your regulation where you expect it - this is called CCM, or continuous conduction mode. The inductor current doesn't fall to zero, but continuously flows. Your duty cycle formula will be valid here.
20 kHz is very slow for a boost converter. 14A peak inductor current is also unrealistic. Most PFC boost converters operate from 70 to 100 kHz. Lower frequency converters generally need larger inductors. If you want to achieve CCM at 20kHz, you'll need a much larger boost inductance value. Try 470uH in your simulation and you'll see the voltage closer to 12V. (If you had a controller in your model, it would automatically adjust the duty cycle to achieve 12V regardless of CCM or DCM operation).
Because your converter is so heavily into DCM, the switching node voltage resembles the output voltage. If you get closer to CCM, you'll see a clearer picture.
For this simulation, the capacitor is sized such that the switch on-time voltage sag (caused by the load) isn't excessive. In real life, there are other parameters that matter (overall loop stability, ripple current and life rating) that you must consider, along with proper MOSFET choice, reverse recovery and softness of the boost diode...
Are you sure you want two NMOS's to do this? It would be much simpler if you used a PMOS. Otherwise, it's not terribly surprising you're getting cross conduction since Vgs depends on the source voltage as well as the gate voltage. Even if the gate pulse goes negative, if the source voltage on the top MOSFET goes even lower than that, then you'll still get conduction when you didn't want it to.
If you want to stick with two NMOS's then you'll need to ensure that the gate voltage of the top NMOS stays at the source voltage if you want it off. You may want to add plots to this question showing Vg and Vs of both MOSFETs so that we can make a more concise answer.
Best Answer
The body diode of the NMOS is conducting, clamping the voltage to 620 mV when the PMOS is turned on (also conducting).
You should rotate the NMOS 180 degrees as shown in left picture. But to draw a schematic correctly, you should actually put Vcc on top, and GND at the bottom (right picture).
Note the pictures for the mosfets in LTspice have the both an arrow. If you cut the arrow loose from the gate and reconnect it to the other terminal of the mosfet (drain) the arrow shows how the body diode is connected (shown in red in left picture).