Electronic – SPI Chip Select for different slaves

(Hopefully) Useful suggestions and comments: -

Your clock speed is not unreasonable but you have to maintain shape so some care in using line drivers and receivers is needed. Another thing you have to watch out for is that when you poll a slave, it will respond synchronized with the clock it receives and drivers and cable introduce delay.

No problem at the slave end but when the reply is sent from the slave, the total delay up and down the line may, on fast clocks push the received symbol too much out of skew with the clock the master is using to "collect" the data. Something to watch out for.

Regarding your 4:16 line CE idea - the slaves are intelligent, why don't you embed an address into each slave and the master transmission then, only the correct slave will respond. It's a little more overhead but I get the impression is isn't a critically fast application. This of course is taking you down a kind of synchronized RS485 scheme which leads me to ask why this isn't considered for your application; running unsynchronized will not cause clock skew errors and at your data rate, 10 metres is easy.

First, you have identified a really annoying part of SPI on the AVR: Connecting SPI slaves will interfere with the proper operation of ICSP.

Second: The SPI bus has MISO, MOSI, and a chip select pin. You can break out the MISO, MOSI and GND pins, and perhaps VCC, plus a different CS pin for each daughter board you want to connect. As long as the CS is not active for the daughter boards, and the daughter board chips do not try to use the bus in master mode, you should be OK.

Third: You can use a buffer chip of some sort (perhaps 74HC125 or similar) with a tri-state function to isolate the ICSP feature from the SPI-talking-to-slaves feature; set the buffer chip up to require a particular pin high to let signals through, and use software to pull that pin high only when your code wants to talk to the slaves, and keep it low after a code reset.