Electronic – SPI on PIC24H not progressing

picspi

I am trying to setup the SPI1 port on my PIC24HJ206GP256 micro. I have set the SPI1CON1 control register with 0x0020, the SPI1STAT control register with 0x8000 (i.e. turn on the SPIEN), and SPI1CON2 = 0.

At the moment a simple write to the SPI1BUF is implemented like this:

 void writeSPI1(char data){
     _SPI1IF = 0;             //set interrupt flag to zero
     SPI1BUF = data;          //write data to SPI1BUF
     while( _SPI1IF == 0);    //wait to flag to go high
 }

When the data is written, the SPI1IF should go high, but it never reaches this point so the program simply remains in the loop forever. So it seems no data will ever be clocked out of the SPI port through MOSI.

I have tried to make it work by setting TRISF = 0x0000, although I have read that the SPI port should take care of SPI pin configuration.

I am using a watch window to view the contents of the SPI1BUF.

I have tried with different settings within the control registers but have had no luck. Also have tried enabling the SPI1IF (IEC0: Interrupt Enable Control Register 0) and still the problem persists.

Are there any extra configurations I have forgotten, like some odd functionality of PORTF which takes precedence over the SPI port?

Best Answer

Use the SPI peripheral library, it'll make things much easier.

Check the data sheet for the alternative functions of the pins you are using. If they are shared with the ADC that will be the default function and you will need to enable them for digital I/O.

You should use the Microchip forums for this type of question, many more people there will be using the 16-bit PICs.

Related Solutions

Electronic – SPI communication

Yes, the slave will keep shifting one data bit in and out on each clock pulse as long as SS is low. When SS goes high the data which is in the shift register at that time will be latched.

A FIFO never needs to be full. It will accept a new byte of data the SPI master shifts in as long as it isn't full. As long as there's data in the FIFO you will read. When the FIFO is empty a read from it should return all zeros.

I would suggest you try to use the SPI in non-FIFO mode. FIFO mode is disabled by setting the SPIFFEN bit to 0 in the SPIFFTX register.

edit re your comment
There is no standard for what should happen if the master clocks new data in when there's none available; SPI doesn't occupy itself with you data content, it's basically just a shift register. The most sensible thing to do is sending zeros, but you could also be sending the last data from the FIFO again. Your protocol should avoid this kind of situation. Does the master really expect to read data, or is it only sending, ignoring data coming in? If it expects data, why isn't it there?

About the 8-bit format section 1.4.2 on page 17 says:

Data must be left-justified when written to SPIDAT and SPITXBUF.
Data read back from SPIRXBUF is right-justified.
SPIRXBUF contains the most recently received character, right-justified, plus any bits that remain from previous transmission(s) that have been shifted to the left.

This indicates that the full 16-bit shift registers are used, but that only 8 clock pulses are generated.

Configuring SPI on PIC16LF1827

As I've just done this I feel I should add to Olin's answer with some code. SPI is terribly simple but you do have to wait for it! There are also application notes warning you to read the buffer and, if you don't need the byte, don't use it. I believe that might be PIC dependent.

Before this code starts, I clear any possible errors by clearing SSPOV, WCOL and BF. Just in case!

    ; == This is an SPI transmit from FSR1 ==
    ;
    ;   nbytes contains the 8 bit number of bytes to send
    ;   We are not interested in the received bytes and we
    ;   poll until completion (SPI is very fast)

Xfer_transmit:

    banksel     SSP1BUF
    moviw       FSR1++
    movwf       SSP1BUF                 ; ssp1buf = *fsr1++

    ifbclr      SSP1STAT, BF            ; Wait for transfer to complete
      jmp       $-1

    movf        SSP1BUF, W              ; Clear BF. Discard data.

    banksel     nbytes
    decfsz      nbytes, F
      jmp       Xfer_transmit

    ; Transmit complete.

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