Electronic – Structural D flip flop in Verilog

fpgaverilog

module dFlipFlop(
    input clk,
    input d,
    output q
    );
wire w1,w2,q_n;

assign w1 = ~(d & clk);
assign w2 = ~(~d & clk);

assign q = ~(w1 & q_n);
assign q_n = ~(w2 & q);

endmodule

will this module work as a D flip flop on my fpga? Any suggestions? I dont currently have my FPGA, but im trying to figure out if this design is worthy or not.

Best Answer

It might work, but it's hard to say what the synthesizer will do with that. It is a much better idea to use an always block when you want to do use a clock.

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