Electronic – switching noise from ltc3780

I think you'll have problems with your layout. C3/C4 MUST be closer to pin 1 (EDIT this should read pins8/9 not pin1). When I say closer I mean living on it! Ditto C7 - it needs to be camped right on pin 7. Now I've never used this part but this is standard procedure for this type of device.

Think about the current pulses flowing from pin 7 to C7 and the length of track between it and the IC - probably 20nH of track.

The ground return of C7 - where is it going? It's going right back to the wrong ground pin (signal ground). C7's ground should be as short as possible to pins 5 and 13 as possible without breaking trespass laws. And this should be your star-point for keying off signal ground. Signal ground should then go to your feedback components and not pass any load or C7 current at all.

I would decline testing this PCB if it was handed to me. Sorry for being abrupt but these are golden rules on switching circuits: -

Yes, there are stability issues and a brief moment when both FETs are on but the beauty of using a FET on the pull-down part of the circuit (i.e. a synchronous buck converter) instead of a schottky diode is this: -

1. Whatever duty cycle your PWM is the output voltage stays constant as a fraction of input voltage - you are in effect using the L and C on the output as a low pass filter to a square wave input.
2. Whatever load you have connected, providing the FETs are lowish on resistance, within reason you don't need to change the PWM mark-space ratio.
3. It will be more efficient on heavier loads than a non-synchronous buck regulator but the down-side is that on light loads it will be less efficient because you need current to drive the N channel FET because of gate capacitance.

I'd also advocate building a 555 timer sawtooth generator as the basis of your system. Something like this: -

I'd then feed it into a fast comparator and then the use the comparator output to drive the two FETs. The two FETs can be "time segregated" with a small RC time delay on the output of the comparator - the undelayed output and the delayed output would feed an AND gate for one of the gate drives and the the same for the other gate drive but using a NOR gate. Plan on maybe 50ns time delay introduced.

What you get is a half-decent synchronous buck convertor that just needs an input to the other comparator input to get the required duty cycle changes. OK so far? Then you can apply a simple control loop that lowers the 2nd input to the comparator as the input voltage gets bigger. Get this working and then apply another small control loop that actually regulates the PWM with load current changes a tad and this would probably work and no negative feedback involved.

Then, as the final touch, and with care and subtlety apply an overall control loop to keep the output better stabilized but remember, with a sync buck you can pretty much get half-decent stable performance without control loops that use negative feedback - if you are wanting to go this approach I can recommend it.

However, for me, I'd just call on Linear Technology and get the device that already does the job.