Electronic – System Verilog generic modules and unused ports

system-verilogvivado

I have written a parametrized FIFO for reuse. Since I want to use the FIFO in multiple places I added several output signals for the fill state, like full, empty, almostFull and almostEmpty.

However sometimes not all of the output signals are used, resulting in warnings about unused signals and that the associated logic will be removed. These warnings clutter the message pane.

Question

What is the correct way to design a generic module like a FIFO, and avoid
warnings about unused ports (while using interfaces for the connection)?

Related questions:

I do not think https://stackoverflow.com/a/22272949/258418 is the way to go, since I am happy for the synthesis tool to rip it out, I simply don't want a warning for dead code removal.

While How to remove this warning in Verilog? looks related, it does not help, since I can't just remove the offending logic/wires, since they might be used by other instances of the code.

Best Answer

There is nothing in the SystemVerilog language that allows you to specify outputs that are allowed to be left unconnected. And you don't want to globally turn off dead code removal warnings because that could mask much larger problems. I see three possible choices:

Write a script that filters your messages to eliminate the warnings from the dead logic that is OK to remove.
Create separate versions of your FIFO with different sets of outputs and instantiate the correct version depending on which version is needed. I realize this goes against the generic solution you are looking for, but the use of macros or submodules might make it a little more reusable.
Live with it the way the messages are now.

Related Solutions

Electronic – System Verilog seq.ended or seq.triggered

Based on the IEEE Std 1800-2005, ended is used inside an assertion, property, or another sequence (§ 17.7.10, ex @(posedge clk) reset ##1 inst ##1 my_seq.ended). triggered is is the equivalent to ended and is allowed outside of an assertion (§ 10.11, ex wait(my_seq.triggered)).

ended has been depreciated in IEEE Std 1800-2012 as mentioned in § C.2.3:

IEEE Std 1800-2005 17.7.3 required using the sequence method ended in sequence expressions and the sequence method triggered in other contexts. Since these two constructs have the same meaning but mutually exclusive usage contexts, in this version of the standard, the triggered method is allowed to be used in sequence expressions, and the usage of ended is deprecated and does not appear in this version of the standard.

Few if any simulators are 1800-2012 complaint, so follow with 1800-2005 for now.

Electronic – Instantiating multidimensional array in system verilog

First off, it is a common practice that parameters are upper case. When reading code this helps identify constants from variables. For arrays, refer to IEEE Std 1800-2012 § 7.4 Packed and unpacked arrays.

Packed means all the bits can be accessed at once or sliced
Unpacked means each index must be individually selected.

The following have the same dimensions:

logic [N-1:0] arr_up [M-1:0]; is M unpacked arrays, each with N packed bits
logic arr_uu [M-1:0] [N-1:0]; is M unpacked arrays, each with N unpacked single bits arrays
logic [M-1:0] [N-1:0] arr_pp; is M-by-N packed array, a slice of N-bits can be read out of the M index

Unpacked arrays can be initialized with a single digit: logic [N-1:0] arr_up [M]; is equivalent to logic [N-1:0] arr_up [0:M-1];. Do note that the [M] is [0:M-1] not [M-1:0].

The differences is in the access. All can access a single bit, but only packed bits can access a slice.

arr_up[M-2] = {{N{1'b0}}}; // legal
arr_uu[M-2] = {{N{1'b0}}}; // illegal, assigning packed to unpacked
arr_pp[M-2] = {{N{1'b0}}}; //legal`

arr_up[M-1:M-4] = {{3*N{1'b1}}}; // illegal, unpacked cannot use sliced array
arr_uu[M-1:M-4] = {{3*N{1'b1}}}; // illegal, unpacked cannot use sliced array
arr_pp[M-1:M-4] = {{3*N{1'b1}}}; // legal

arr_up[M-2][N-5] = 1'b0; // legal
arr_uu[M-2][N-5] = 1'b0; // legal
arr_pp[M-2][N-5] = 1'b0; // legal

arr_up[M-2][N-5:4] = {{N-9{1'b1}}}; // legal
arr_uu[M-2][N-5:4] = {{N-9{1'b1}}}; // illegal, unpacked cannot use sliced array
arr_pp[M-2][N-5:4] = {{N-9{1'b1}}}; // legal

If the simulator is only accessing a single bit or index, unpacked arrays will give better performance. This is because packed arrays are accessed as a whole even if only one bit is being used. There is a balance between the simulators lookup overhead and number of lookup operations. Generally 2-D arrays are unpacked arrays of packed arrays. Adding dimensions is normal on the unpacked side. bytes, integers, words, and data buses are packed.

With typedef enum logic [N-1:0][1:0]{S0,S1,S2,S3} statetype;, be aware this is creating the definition of the state type. It is create a 2*N-bit array but only allows 4 values.

For an array of 4-state state machines, I would recommend:

typedef enum logic [1:0]{S0,S1,S2,S3} state_et;
state_et state[N], nextstate[N];

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Related Solutions

Electronic – System Verilog seq.ended or seq.triggered

Electronic – Instantiating multidimensional array in system verilog

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