Electronic – System verilog synthesis in Vivado

system-verilogverilogvivado

I am trying to synthesis system verilog (.sv) file in vivado. The file uses defines from another verilog (.v) file. This combination is not working. I tried renaming define file into *.sv then the error got resolved.

Is there such constraint that all defines for system verilog should be in another system verilog file ?

If no, what is the best way to resolved this issue ? I dont want to rename the file since it is part of release from different team. Please help.

Let know if you need further info on this.

Regards,

Tollin

Best Answer

Vivado Synthesis Guide guide mentions about this issue in page 260:

Targeting SystemVerilog for a Specific File

By default, the Vivado synthesis tool compiles *.v files with the Verilog 2005 syntax and *.sv files with the SystemVerilog syntax. To target SystemVerilog for a specific *.v file in the Vivado IDE, right-click the file, and select Source Node Properties. In the Source File Properties window, change the File Type to SystemVerilog, and click OK.

TCL Command to Set Properties

Alternatively, you can use the following Tcl command in the Tcl Console:

set_property file_type SystemVerilog [get_files <filename>.v]

Related Solutions

System verilog on Quartus synthesis issue

When you type

y=x|c;
x=a&b;

it means that you want to calculate y = x|c, then you want to set x to a&b. Since this must be implemented with gates, the old value of x must be stored until the end of the clock cycle, hence the extra flip-flop. If you rewrote this with nonblocking assignments, you would do:

y<=x|c;
x<=a&b;

However, when you write

x=a&b;
y=x|c;

it means calculate x, then calculate y with the new value of x. If you wanted to implement this with nonblocking assignments, you would do:

x<=a&b;
y<=(a&b)|c;

You could also use an assign statement to set x earlier, or mix a blocking and a nonblocking assignment. In this case, if the registered x value is never used, the flip flop will be deleted automatically by the optimizer.

Electronic – System Verilog generic modules and unused ports

There is nothing in the SystemVerilog language that allows you to specify outputs that are allowed to be left unconnected. And you don't want to globally turn off dead code removal warnings because that could mask much larger problems. I see three possible choices:

Write a script that filters your messages to eliminate the warnings from the dead logic that is OK to remove.
Create separate versions of your FIFO with different sets of outputs and instantiate the correct version depending on which version is needed. I realize this goes against the generic solution you are looking for, but the use of macros or submodules might make it a little more reusable.
Live with it the way the messages are now.

Best Answer

Targeting SystemVerilog for a Specific File

TCL Command to Set Properties

Related Solutions

System verilog on Quartus synthesis issue

Electronic – System Verilog generic modules and unused ports

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