System verilog on Quartus synthesis issue

synthesissynthesizersystem-verilog

module blockingbad(input logic clk,a,b,c,output logic y);
    logic x;

    always_ff @(posedge clk) begin
    y=x|c;
    x=a&b;
    end
    endmodule

enter image description here

For the above Sysverilog snippet, the quartus 13.1 synthesizes a netlist shown above.

But when I interchange the ordering of calculation of y and x, I get a synthesized netlist shown below.

enter image description here

Why exactly am I getting a different netlist? I know it has got to do with the blocking assignment "=" but I can't understand the change in number of flip flops. Can anybody explain it to me.
Thanks

Best Answer

When you type

y=x|c;
x=a&b;

it means that you want to calculate y = x|c, then you want to set x to a&b. Since this must be implemented with gates, the old value of x must be stored until the end of the clock cycle, hence the extra flip-flop. If you rewrote this with nonblocking assignments, you would do:

y<=x|c;
x<=a&b;

However, when you write

x=a&b;
y=x|c;

it means calculate x, then calculate y with the new value of x. If you wanted to implement this with nonblocking assignments, you would do:

x<=a&b;
y<=(a&b)|c;

You could also use an assign statement to set x earlier, or mix a blocking and a nonblocking assignment. In this case, if the registered x value is never used, the flip flop will be deleted automatically by the optimizer.

Related Solutions

Electronic – Generic free Verilog synthesis tools

Yosys does exactly what you want and supports a large portion of Verilog-2005. Have a look at the */rtl/ directories at https://github.com/cliffordwolf/yosys-bigsim/ for examples that can be synthesized with Yosys.

Disclosure: I am the author of Yosys.

Electronic – Quartus II ignoring synthesis attribute noprune

Despite the "reg" declaration in the source code, you have not in fact created any registers. The behavior of your 3000-bit "data" bus is simply that its value is a function of the current value of the "button" input; it doesn't depend on the past history of that or any other signal, so there's no actual memory behavior specified, and therefore no synthesizable flip-flops.

The only logic here is a simple inverter, the output of which is replicated 3000 times. Since nothing is connected to the "data" bus (and it isn't even specified as an output port of the module), there's no need to implement logic to support the fanout, and in fact, there's no need to implement the inverter at all. What is it you're actually trying to debug? By what mechanism were you hoping to observe the data bus?

I'm guessing that Xilinx took an ultra-conservative approach and actually implemented 3000 inverters. I have no idea why it would do that. The answer may have something to do with the actual debug mechanisms that each manufacturer builds into its chips.

If you're trying to measure things like power consumption for various levels of FPGA utilization, the usual technique for this is to create a long shift register. The register is clocked by common clock signal (usually a global clock) and the input of the first bit and the output of the last bit are brought out to pins (the latter is so that the synthesis software doesn't "prune" away the entire chain).

You control the amount of resouce utilization by varying the length of the shift register, and you control the amount of switching activity by the pattern that you shift into it. A pattern of all zeros or all ones eventually has the minimum activity, while a pattern of alternating ones and zeros eventually ramps up to the maximum level of activity.

module shift (clk, si, so);
  parameter SHIFT_LENGTH = 3000;
  input     clk, si;
  output    so;
  reg    [SHIFT_LENGTH-1:0] data;
  always @(posedge clk) begin
    data <= {data[SHIFT_LENGTH-2:0], si};
  end
  assign so = data[SHIFT_LENGTH-1];
endmodule

Best Answer

Related Solutions

Electronic – Generic free Verilog synthesis tools

Electronic – Quartus II ignoring synthesis attribute noprune

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