I use the following tools which all have full library support:
- Riviera-PRO (from at least version 2006.02 onwards)
- Xilinx ISE (from at least version 10 onwards)
- Quartus (from at least version 10.0 onwards; Two or more entities with the same name cannot be used, however, only packages)
- Synplify (from at least version 9.0 onwards)
The only caveat is that the XST tool in the Xilinx toolchain is incapable of performing automatic file ordering on projects where entity names exist in multiple libraries (it ungraciously gets stuck looping forever trying to resolve dependencies).
I am not sure why you need a special option, the use of memories are pretty standard for use inside modules. Unless you are trying to imply a special low area/power cell similar to a ram.
For a standard memory it is just the same as having multiple regs. memory does not imply RAM the same way reg does not automatically imply flip-flop.
The 'memory.list' is a plain text file which contains the values which you want to load in to the memory, this is not required if you just wanted to reset the memory and have every element at 0.
memory.list should look like :
//Comments are allowed
1100_1100 // This is first address i.e 8'h00
1010_1010 // This is second address i.e 8'h01
@ 55 // Jump to new address 8'h55
0101_1010 // This is address 8'h55
0110_1001 // This is address 8'h56
The use of the file would then follow :
module memory();
reg [7:0] my_memory [0:255];
initial begin
$readmemh("memory.list", my_memory);
end
endmodule
alternatively :
module memory();
reg [7:0] my_memory [0:255];
integer i;
initial begin
for( i=0; i<256; i=i+1) //Can be statically unrolled
my_memory[i] = 8'h00 ;
end
endmodule
If using as a bank of flip-flops with async-reset:
module memory(
input clk,
input rst_n,
input [7:0] addr_wr,
input [7:0] data_wr
);
reg [7:0] my_memory [0:255];
integer i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
for( i=0; i<256; i=i+1) //Can be statically unrolled
my_memory[i] <= 8'h00 ;
end
else begin
my_memory[addr_wr] <= data_wr ;
end
end
endmodule
Best Answer
Yosys does exactly what you want and supports a large portion of Verilog-2005. Have a look at the */rtl/ directories at https://github.com/cliffordwolf/yosys-bigsim/ for examples that can be synthesized with Yosys.
Disclosure: I am the author of Yosys.