Verilog code synthesis error

I'm having problem with my verilog code when I synthesize it. It shows multiple drivers error. I think may be it's because of multiple always blocks I'm using in it. So how can I fix it!!? Here it is:

module check(csx,dcx,wrx,rdx,clk,d_out,res);
input wire clk,res;
output reg csx,dcx,wrx,rdx;
output reg [7:0]d_out;
reg [2:0]count;

always @ (res)
begin
  if (res==1)
  begin
    csx=1;
    wrx=0;
    rdx=1;
    dcx=0;
    count=0;
    d_out=0;
  end
end

always @ (posedge clk)
begin
  count=count+1;
end

always @ (count)
begin
  repeat(3'h5)
  begin
    if((count+res)==3'h2)
    begin
      d_out=8'h28;
    end
    else if(count==3'h3)
    begin
      csx=0;
      wrx=1;
    end
    else if (count==3'h4)
    begin
      wrx=0;
      csx=1;
      d_out=8'h11;
    end
    else if (count==3'h5)
    begin
      csx=0;
      wrx=1;
    end
  end
end

endmodule